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mb9a b 40 nb series 32 - bit arm ? cortex ? - m3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05631 rev * b revised july 26, 2017 the mb9ab40nb series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with low - power consumption mode and competitive cost. these series are based on the arm cortex - m3 processor with on - chip flash memory and sram, and have p eripheral functions such as various timers, adcs, lcdc and communication interfaces (usb, uart, csio, i 2 c). the products which are described in this data sheet are placed into type6 product categories in fm3 family peripheral manual. features 32 - bit arm cortex - m3 core ? processor version: r2p1 ? up to 40 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? dual operation flash memory ? dual operation flash memory has the upper bank and the lower bank. so, this series could implement erase, write and read operations for each bank simultaneously. ? main area: up to 256 kbytes (up to 240 kbytes upper bank + 16 kbytes lower bank) ? work area: 32 kbyte s (lower bank ) ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series on - chip sram is composed of two independent sram (sram0, sram1). sram 0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 16 kbyte s ? sram1: up to 16 kbyte s external bus interface * ? supports sram, nor flash memory device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size : up to 256 mbytes ? supports address/data multiplex ? supports external rdy function *: mb9afb41lb, fb42lb and fb44lb do not support external bus interface. usb i nterface the usb interface is composed of device and host. pll for usb is built - in, usb clock can be generated by multiplication of main clock. [usb device ] ? usb2.0 full - speed supported ? max 6 endpoint supported ? endpoint 0 is control transfer ? endpoint 1, 2 can select bulk - transfer, interrupt - transfer or isochronous - tra nsfer ? endpoint 3 to 5 can select bulk - transfer or interrupt - transfer ? endpoint 1 to 5 is comprised of double buffers. ? the size of each endpoint is according to the follows. ? endpoint 0, 2 to 5: 64 bytes ? endpoint 1: 256 bytes [usb host] ? usb2.0 full/low - speed supported ? bulk - transfer, interrupt - transfer and isochronous - transfer support ? usb device connected/disconnected automatic detection ? automatic processing of the in/out token handshake packet ? max 256 - byte packet - length supported ? wake - up function supported lcd c ontroller ( lcdc ) ? up to 40 seg 8 com ? 8 com or 4 com mode can be selected. ? built - in internal dividing resistor ? lcd drive power supply (bias) pin (vv4 to vv 0) ? with blinking function
document number: 002 - 05631 rev * b page 2 of 128 mb9a b 40 nb series multi - function s erial i nterface (max 8 channels ) ? 4 channels with 16 steps9 - bit fifo (ch.4 to ch.7), 4 channels without fifo (ch.0 to ch.3) ? operation mode is selectable from the following for each channel. ? uart ? csio ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control * : automatically control the transmission by cts/rts (only ch.4) ? various error detection functions available (parity errors, framing errors, and overrun errors) *: mb9afb41l b , fb42 l b and fb44l b do not support hardware flow control . [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function available [i 2 c] standard - mode (max 100 kbps) / fast - mode (max 400 kbps) supported dma controller (8 channels) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbyte s ) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter (max 24 channels) [ 12 - bit a/d converter ] ? succe ssive approximation type ? built - in 2 unit s ? conversion time: 2 .0 s @ 2.7 v to 3.6 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for priority conversi on: 4 steps) base timer (max 8 channels) operation mode is selectable from the following for each channel . ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer general - purpose i/o port this series can use its pins as general - purp ose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in . it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level d irectly ? built - in the port relocate function ? up to 8 3 fast general - purpose i/o ports@1 0 0 pin package ? some ports are 5 v tolerant. s ee pin assignment to confirm the corresponding pins. dual timer (32 - /16 - bit down cou nter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the following for each channel . ? free - running ? periodic (=reload) ? one - shot hdmi - cec/remote control receiver ( up to 2 channel s) [hdmi - cec transmitter ] ? header block a utomatic transmission by judging signal free ? generating status interrupt by detecting arbitration lost ? generating start, eom, ack automatically to output cec transmission by setting 1 byte data ? generating transmission status interrupt when transmitting 1 block (1 byte data and eom/ack) [hdmi - cec receiver ] ? automatic ack reply function available ? line error detection function available [remote control receiver ] ? 4 bytes reception buffer ? repeat code detection function available
document number: 002 - 05631 rev * b page 3 of 128 mb9a b 40 nb series real - time clo ck (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 0 0 to 99. ? the interrupt function with specifying date and time (year/month/day/hour/minute) is available. this function is also available by specifying only yea r, month, day, hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time with continuing the time count. ? leap year automatic count is available. watch counter ? the watch counter is used for wake up from sleep an d timer mode. ? interval timer: up to 64 s (max) @ sub clock: 32.768 khz external interrupt controller unit ? up to 16 external interrupt input pins ? include one non - maskable interrupt (nmi) input pin watchdog t imer (2 channels) ? a watchdog timer can generate in terrupts or a reset when a time - out value is reached. ? this series consists of two different watchdogs, a hardware watchdog and a software watchdog. ? the hardware watchdog timer is clocked by the built - in low - speed cr oscillator. therefore , the hardware watc hdog is active in any low - power consumption modes except rtc, stop , deep standby rtc, deep standby stop modes . crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduc tion of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset [clocks] ? selectable from five clock sources (2 external oscillator s, 2 built - in cr oscillators , and main pll). ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? built - in high - speed cr clock: 4 mhz ? built - in low - speed cr clock: 100 khz ? main pll clock [resets] ? reset requests from i nitx pin ? power on reset ? software reset ? watchdog timers reset ? low - voltage detection reset ? clock super visor reset clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? external clock fa ilure (clock stop) is detected, reset is asserted. ? external frequency anomaly is detected, interrupt or reset is asserted. low - voltage consumption detector (lvd) ? this series include s 2 - stage monitoring of voltage on the vcc pins. when the voltage falls bel ow the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption m ode ? six low - power consumption modes supported. ? sleep ? timer ? rtc ? stop ? deep standby r tc (selectable between k eeping the value of ram and not) ? deep standby stop (selectable between k eeping the value of ram and not) debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm).* *: mb9afb41l b /m b , fb42l b /m b , fb44l b /m b support on ly swj - dp. unique id unique value of the device (41 - bit) is set. power supply wide range voltage: vcc = 1.65 v to 3.6 v vcc = 3.0 v to 3.6 v (when usb is used) vcc = 2. 2 v to 3.6 v (when lcdc is used)
document number: 002 - 05631 rev * b page 4 of 128 mb9a b 40 nb series contents features ................................ ................................ ................................ ................................ ................................ .......... 1 1. product lineup ................................ ................................ ................................ ................................ ...................... 6 2. packages ................................ ................................ ................................ ................................ ................................ 7 3 . pin assignment ................................ ................................ ................................ ................................ ..................... 8 4. list of pin functions ................................ ................................ ................................ ................................ ........... 15 4.1 list of pin numbers ................................ ................................ ................................ ................................ ............ 15 4.2 list of pin functions ................................ ................................ ................................ ................................ ........... 26 5. i/o circuit type ................................ ................................ ................................ ................................ .................... 41 6. handling precautions ................................ ................................ ................................ ................................ ......... 48 6.1 precautions for product design ................................ ................................ ................................ .......................... 48 6.2 precautions for package mounting ................................ ................................ ................................ ..................... 49 6.3 precautions for use e nvironment ................................ ................................ ................................ ....................... 51 7. handling devices ................................ ................................ ................................ ................................ ................ 52 8. block diagram ................................ ................................ ................................ ................................ ..................... 54 9. memo ry size ................................ ................................ ................................ ................................ ........................ 54 10. memory map ................................ ................................ ................................ ................................ ........................ 55 11. pin status in each cpu state ................................ ................................ ................................ ............................. 58 12. list of pin status ................................ ................................ ................................ ................................ ................. 59 13. electrical characteristics ................................ ................................ ................................ ................................ ... 66 13.1 absolute maximum ratings ................................ ................................ ................................ ................................ 66 13.2 recommended operating conditions ................................ ................................ ................................ ................. 67 13.3 dc characteristics ................................ ................................ ................................ ................................ .............. 68 13.3.1 current rating ................................ ................................ ................................ ................................ ...................... 68 13.3.2 pin characteristics ................................ ................................ ................................ ................................ .............. 71 13.4 lcd characteristics ................................ ................................ ................................ ................................ ............ 72 13.5 ac cha racteristics ................................ ................................ ................................ ................................ .............. 73 13.5.1 main clock input characteristics ................................ ................................ ................................ ......................... 73 13.5.2 sub clock input characteristics ................................ ................................ ................................ .......................... 74 13.5.3 built - in cr oscillation characteristics ................................ ................................ ................................ ................. 74 13.5.4 operating conditions of main and usb pll ................................ ................................ ................................ ....... 75 13.5.5 reset input characteristics ................................ ................................ ................................ ................................ . 76 13.5.6 power - on reset timing ................................ ................................ ................................ ................................ ....... 77 13.5.7 external bus timing ................................ ................................ ................................ ................................ ............ 78 13.5.8 base timer input timing ................................ ................................ ................................ ................................ ..... 85 13.5.9 csio/uart timing ................................ ................................ ................................ ................................ ............. 86 13.5.10 external inpu t timing ................................ ................................ ................................ ................................ ....... 94 13.5.11 i 2 c timing ................................ ................................ ................................ ................................ ........................ 95 13.5.12 etm timing ................................ ................................ ................................ ................................ ..................... 96 13.5.13 jtag timing ................................ ................................ ................................ ................................ .................... 97 13.6 12 - bit a/d converter ................................ ................................ ................................ ................................ ........... 98 13.7 usb characteristics ................................ ................................ ................................ ................................ ......... 101 13.8 low - voltage detection characteristics ................................ ................................ ................................ ............. 105 13.8.1 interrupt of low - voltage detection ................................ ................................ ................................ .................... 106 13.9 flash memory write/er ase characteristics ................................ ................................ ................................ ...... 107 13.9.1 write / erase time ................................ ................................ ................................ ................................ .............. 107 13.9.2 write cycles and data hold time ................................ ................................ ................................ ........................ 107 13.10 return time from low - power consumption mode ................................ ................................ ........................... 108 13.10.1 return factor: interrupt/wkup ................................ ................................ ................................ ...................... 108 13.10.2 return factor: reset ................................ ................................ ................................ ................................ ..... 109 14. ordering information ................................ ................................ ................................ ................................ ........ 111
document number: 002 - 05631 rev * b page 5 of 128 mb9a b 40 nb series 15. package dimensions ................................ ................................ ................................ ................................ ........ 112 16. errata ................................ ................................ ................................ ................................ ................................ .. 121 16.1 part numbers affected ................................ ................................ ................................ ................................ ..... 121 16.2 qualification status ................................ ................................ ................................ ................................ ........... 121 16.3 errata summary ................................ ................................ ................................ ................................ ............... 121 17. major changes ................................ ................................ ................................ ................................ .................. 125 document history ................................ ................................ ................................ ................................ ...................... 127 sales, solutions, and legal information ................................ ................................ ................................ .................. 128
document number: 002 - 05631 rev * b page 6 of 128 mb9a b 40 nb series 1. product lineup memory size product name mb9afb41l b /m b /n b mb9afb42l b /m b /n b mb9afb44l b /m b /n b on - chip flash memory main area 64 kbytes 128 kbytes 256 kbytes work area 32 kbytes 32 kbytes 32 kbytes on - chip s ram sram0 8 kbytes 8 kbytes 16 kbytes sram1 8 kbytes 8 kbytes 16 kbytes total 16 kbytes 16 kbytes 32 kbytes function product name mb9afb41lb mb9afb42lb mb9afb44lb mb9afb41mb mb9afb 42mb mb9afb44mb mb9afb41nb mb9afb42nb mb9afb44nb pin count 64 80/96 100/112 cpu cortex - m3 freq. 40 mhz power supply voltage range 1.65 v to 3.6 v usb2.0 ( device /host) 1 ch . dmac 8 ch. external bus interface - addr: 21 - bit (max) r/w data: 8 - bit (ma x) cs: 4 (max) support : sram , nor flash memory addr: 25 - bit (max) r/w data: 8 - /16 - bit (max) cs: 8 (max) support : sram , nor flash memory lcd controller 20 seg 8 com (max ) 33 seg 8 com (max) 40 seg 8 com (max) mf serial interface (uart/csio/i 2 c) 8 c h. (max) ch . 4 to ch . 7: fifo (16 steps 9 - bit) ch . 0 to c h . 3: no fifo base timer (pwc/reload timer/pwm/ppg) 8 ch. (max) dual timer 1 unit hdmi - cec/ remote control receiver 2 ch. (max) real - time clock 1 unit watch counter 1 unit crc accelerator yes wa tchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 8 pins (max) + nmi 1 11 pins (max) + nmi 1 16 pins (max) + nmi 1 i/o ports 51 pins (max) 66 pins (max) 83 pins (max) 12 - bit a/d converter 12 ch . (2 unit s ) 17 ch . (2 unit s ) 24 ch . (2 unit s ) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp swj - dp/etm unique id yes note: ? all signals of the peripheral function in each product cannot be allocated by limiting t he pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. ? see electrical characteristics 12.5 ac characteristics 12.5.3 built - in cr oscillation characteristics for accuracy of built - in cr .
document number: 002 - 05631 rev * b page 7 of 128 mb9a b 40 nb series 2. packages product name package mb9afb41lb mb9afb42lb mb9afb44lb mb9afb41mb mb9afb42mb mb9afb44mb mb9afb41nb mb9afb42nb mb9afb44nb lqfp: lqd064 (0.5mm pitch) ? - - lqfp: lqg064 (0.65mm pitch) ? - - qfn: vnc064 (0.5mm pitch) ? - - ? lqfp: lqh080 (0.5mm pitch) - ? - lqfp: l qj080 (0. 6 5mm pitch) - ? - bga: fdg096 (0.5mm pitch) - ? ? - lqfp: lqi100 (0.5mm pitch) - ? - ? qfp: pqh100 (0.65mm pitch) - ? - ? bga: lbc112 (0.8mm pitch) - ? - ? ? : supported note: ? see package dimensions for detail ed information on each package.
document number: 002 - 05631 rev * b page 8 of 128 mb9a b 40 nb series 3. pin assignment lqi100 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same functi on for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 vcc p60/sin5_0/tioa2_2/int15_1/wkup3/cec1/mrdy_1 p61/sot5_0/tiob2_2/uhconx/seg00 p62/sck5_0/adtg_3/seg01/moex_1 p63/int03_0/seg02/mwex_1 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/seg03/mdqm1_1 p0d/rts4_0/tioa3_2/seg04/mdqm0_1 p0c/sck4_0/tioa6_1/male_1 p0b/sot4_0/tiob6_1/mcsx0_1 p0a/sin4_0/int00_2/mcsx1_1 p09/traceclk/tiob0_2/rts4_2/seg05/mcsx2_1 p08/an23/traced3/tioa0_2/cts4_2/seg06/mcsx3_1 p07/an22/traced2/adtg_0/sck4_2/seg07/mclkout_1 p06/an21/traced1/tiob5_2/sot4_2/int01_1/seg08/mcsx4_1 p05/an20/traced0/tioa5_2/sin4_2/int00_1/seg09/mcsx5_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc 1 75 vss p50/int00_0/sin3_1/vv4/madata00_1 2 74 p20/an19/int05_0/crout_0/seg10/mad24_1 p51/int01_0/sot3_1/vv3/madata01_1 3 73 p21/an18/sin0_0/int06_1/wkup2/seg11 p52/int02_0/sck3_1/vv2/madata02_1 4 72 p22/an17/sot0_0/tiob7_1/seg12 p53/sin6_0/tioa1_2/int07_2/vv1/madata03_1 5 71 p23/an16/sck0_0/tioa7_1/seg13 p54/sot6_0/tiob1_2/vv0/madata04_1 6 70 p1f/an15/adtg_5/mad23_1 p55/sck6_0/adtg_1/seg39/madata05_1 7 69 p1e/an14/rts4_1/seg14/mad22_1 p56/int08_2/seg38/madata06_1 8 68 p1d/an13/cts4_1/seg15/mad21_1 p30/tiob0_1/int03_2/com7/madata07_1 9 67 p1c/an12/sck4_1/seg16/mad20_1 p31/tiob1_1/sck6_1/int04_2/com6/madata08_1 10 66 p1b/an11/sot4_1/seg17/mad19_1 p32/tiob2_1/sot6_1/int05_2/com5/madata09_1 11 65 p1a/an10/sin4_1/int05_1/seg18/mad18_1 p33/int04_0/tiob3_1/sin6_1/adtg_6/com4/madata10_1 12 64 p19/an09/sck2_2/seg19/mad17_1 p34/tiob4_1/madata11_1 13 63 p18/an08/sot2_2/seg20/mad16_1 p35/tiob5_1/int08_1/madata12_1 14 62 avss p36/sin5_2/int09_1/madata13_1 15 61 avrh p37/sot5_2/int10_1/madata14_1 16 60 avcc p38/sck5_2/int11_1/madata15_1 17 59 p17/an07/sin2_2/int04_1/seg21/mad15_1 p39/adtg_2/com3 18 58 p16/an06/sck0_1/seg22/mad14_1 p3a/tioa0_1/rtcco_2/subout_2/com2 19 57 p15/an05/sot0_1/seg23/mad13_1 p3b/tioa1_1/com1 20 56 p14/an04/sin0_1/int03_1/seg24/mad12_1 p3c/tioa2_1/com0 21 55 p13/an03/sck1_1/rtcco_1/subout_1/seg25/mad11_1 p3d/tioa3_1/seg37 22 54 p12/an02/sot1_1/seg26/mad10_1 p3e/tioa4_1/seg36 23 53 p11/an01/sin1_1/int02_1/wkup1/seg27/mad09_1 p3f/tioa5_1/seg35 24 52 p10/an00/seg28 vss 25 51 vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vcc p40/tioa0_0/int12_1 p41/tioa1_0/int13_1 p42/tioa2_0 p43/tioa3_0/adtg_7 p44/tioa4_0/seg34/mad00_1 p45/tioa5_0/seg33/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/int14_1/sin3_2/seg32/mad02_1 p49/tiob0_0/sot3_2/seg31/mad03_1 p4a/tiob1_0/sck3_2/seg30/mad04_1 p4b/tiob2_0/seg29/mad05_1 p4c/tiob3_0/sck7_1/cec0/mad06_1 p4d/tiob4_0/sot7_1/mad07_1 p4e/tiob5_0/int06_2/sin7_1/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 100
document number: 002 - 05631 rev * b page 9 of 128 mb9a b 40 nb series pqh100 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there a re multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. p50/int00_0/sin3_1/vv4/madata00_1 vcc vss p81/udp0 p80/udm0 vcc p60/sin5_0/tioa2_2/int15_1/wkup3/cec1/mrdy_1 p61/sot5_0/tiob2_2/uhconx/seg00 p62/sck5_0/adtg_3/seg01/moex_1 p63/int03_0/seg02/mwex_1 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/seg03/mdqm1_1 p0d/rts4_0/tioa3_2/seg04/mdqm0_1 p0c/sck4_0/tioa6_1/male_1 p0b/sot4_0/tiob6_1/mcsx0_1 p0a/sin4_0/int00_2/mcsx1_1 p09/traceclk/tiob0_2/rts4_2/seg05/mcsx2_1 p08/an23/traced3/tioa0_2/cts4_2/seg06/mcsx3_1 p07/an22/traced2/adtg_0/sck4_2/seg07/mclkout_1 p06/an21/traced1/tiob5_2/sot4_2/int01_1/seg08/mcsx4_1 p05/an20/traced0/tioa5_2/sin4_2/int00_1/seg09/mcsx5_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 vcc vss p20/an19/int05_0/crout_0/seg10/mad24_1 p21/an18/sin0_0/int06_1/wkup2/seg11 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p51/int01_0/sot3_1/vv3/madata01_1 81 50 p22/an17/sot0_0/tiob7_1/seg12 p52/int02_0/sck3_1/vv2/madata02_1 82 49 p23/an16/sck0_0/tioa7_1/seg13 p53/sin6_0/tioa1_2/int07_2/vv1/madata03_1 83 48 p1f/an15/adtg_5/mad23_1 p54/sot6_0/tiob1_2/vv0/madata04_1 84 47 p1e/an14/rts4_1/seg14/mad22_1 p55/sck6_0/adtg_1/seg39/madata05_1 85 46 p1d/an13/cts4_1/seg15/mad21_1 p56/int08_2/seg38/madata06_1 86 45 p1c/an12/sck4_1/seg16/mad20_1 p30/tiob0_1/int03_2/com7/madata07_1 87 44 p1b/an11/sot4_1/seg17/mad19_1 p31/tiob1_1/sck6_1/int04_2/com6/madata08_1 88 43 p1a/an10/sin4_1/int05_1/seg18/mad18_1 p32/tiob2_1/sot6_1/int05_2/com5/madata09_1 89 42 p19/an09/sck2_2/seg19/mad17_1 p33/int04_0/tiob3_1/sin6_1/adtg_6/com4/madata10_1 90 41 p18/an08/sot2_2/seg20/mad16_1 p34/tiob4_1/madata11_1 91 40 avss p35/tiob5_1/int08_1/madata12_1 92 39 avrh p36/sin5_2/int09_1/madata13_1 93 38 avcc p37/sot5_2/int10_1/madata14_1 94 37 p17/an07/sin2_2/int04_1/seg21/mad15_1 p38/sck5_2/int11_1/madata15_1 95 36 p16/an06/sck0_1/seg22/mad14_1 p39/adtg_2/com3 96 35 p15/an05/sot0_1/seg23/mad13_1 p3a/tioa0_1/rtcco_2/subout_2/com2 97 34 p14/an04/sin0_1/int03_1/seg24/mad12_1 p3b/tioa1_1/com1 98 33 p13/an03/sck1_1/rtcco_1/subout_1/seg25/mad11_1 p3c/tioa2_1/com0 99 32 p12/an02/sot1_1/seg26/mad10_1 p3d/tioa3_1/seg37 100 31 p11/an01/sin1_1/int02_1/wkup1/seg27/mad09_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p3e/tioa4_1/seg36 p3f/tioa5_1/seg35 vss vcc p40/tioa0_0/int12_1 p41/tioa1_0/int13_1 p42/tioa2_0 p43/tioa3_0/adtg_7 p44/tioa4_0/seg34/mad00_1 p45/tioa5_0/seg33/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/int14_1/sin3_2/seg32/mad02_1 p49/tiob0_0/sot3_2/seg31/mad03_1 p4a/tiob1_0/sck3_2/seg30/mad04_1 p4b/tiob2_0/seg29/mad05_1 p4c/tiob3_0/sck7_1/cec0/mad06_1 p4d/tiob4_0/sot7_1/mad07_1 p4e/tiob5_0/int06_2/sin7_1/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss vcc p10/an00/seg28 qfp - 100
document number: 002 - 05631 rev * b page 10 of 128 mb9a b 40 nb series lqh080/lqj080 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 vcc p60/sin5_0/tioa2_2/int15_1/wkup3/cec1/mrdy_1 p61/sot5_0/tiob2_2/uhconx/seg00 p62/sck5_0/adtg_3/seg01/moex_1 p63/int03_0/seg02/mwex_1 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0e/cts4_0/tiob3_2/seg03/mdqm1_1 p0d/rts4_0/tioa3_2/seg04/mdqm0_1 p0c/sck4_0/tioa6_1/male_1 p0b/sot4_0/tiob6_1/mcsx0_1 p0a/sin4_0/int00_2/mcsx1_1 p07/an22/adtg_0/seg07/mclkout_1 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_1 p01/tck/swclk p00/trstx/mcsx7_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 1 60 p20/an19/int05_0/crout_0/seg10/mad24_1 p50/int00_0/sin3_1/vv4/madata00_1 2 59 p21/an18/sin0_0/int06_1/wkup2/seg11 p51/int01_0/sot3_1/vv3/madata01_1 3 58 p22/an17/sot0_0/tiob7_1/seg12 p52/int02_0/sck3_1/vv2/madata02_1 4 57 p23/an16/sck0_0/tioa7_1/seg13 p53/sin6_0/tioa1_2/int07_2/vv1/madata03_1 5 56 p1b/an11/sot4_1/seg17/mad19_1 p54/sot6_0/tiob1_2/vv0/madata04_1 6 55 p1a/an10/sin4_1/int05_1/seg18/mad18_1 p55/sck6_0/adtg_1/seg39/madata05_1 7 54 p19/an09/sck2_2/seg19/mad17_1 p56/int08_2/seg38/madata06_1 8 53 p18/an08/sot2_2/seg20/mad16_1 p30/tiob0_1/int03_2/com7/madata07_1 9 52 avss p31/tiob1_1/sck6_1/int04_2/com6/madata08_1 10 51 avrh p32/tiob2_1/sot6_1/int05_2/com5/madata09_1 11 50 avcc p33/int04_0/tiob3_1/sin6_1/adtg_6/com4/madata10_1 12 49 p17/an07/sin2_2/int04_1/seg21/mad15_1 p39/adtg_2/com3 13 48 p16/an06/sck0_1/seg22/mad14_1 p3a/tioa0_1/rtcco_2/subout_2/com2 14 47 p15/an05/sot0_1/seg23/mad13_1 p3b/tioa1_1/com1 15 46 p14/an04/sin0_1/int03_1/seg24/mad12_1 p3c/tioa2_1/com0 16 45 p13/an03/sck1_1/rtcco_1/subout_1/seg25/mad11_1 p3d/tioa3_1/seg37 17 44 p12/an02/sot1_1/seg26/mad10_1 p3e/tioa4_1/seg36 18 43 p11/an01/sin1_1/int02_1/wkup1/seg27/mad09_1 p3f/tioa5_1/seg35 19 42 p10/an00/seg28 vss 20 41 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44/tioa4_0/seg34/mad00_1 p45/tioa5_0/seg33/mad01_1 c vss vcc p46/x0a p47/x1a initx p48/int14_1/sin3_2/seg32/mad02_1 p49/tiob0_0/sot3_2/seg31/mad03_1 p4a/tiob1_0/sck3_2/seg30/mad04_1 p4b/tiob2_0/seg29/mad05_1 p4c/tiob3_0/sck7_1/cec0/mad06_1 p4d/tiob4_0/sot7_1/mad07_1 p4e/tiob5_0/int06_2/sin7_1/mad08_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 80
document number: 002 - 05631 rev * b page 11 of 128 mb9a b 40 nb series lqd064/ lqg064 (top view) note : ? the number after the underscor e ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 vcc p60/sin5_0/tioa2_2/int15_1/wkup3/cec1 p61/sot5_0/tiob2_2/uhconx/seg00 p62/sck5_0/adtg_3/seg01 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0c/sck4_0/tioa6_1 p0b/sot4_0/tiob6_1 p0a/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/an18/sin0_0/int06_1/wkup2/seg11 p50/int00_0/sin3_1/vv4 2 47 p22/an17/sot0_0/tiob7_1/seg12 p51/int01_0/sot3_1 3 46 p23/an16/sck0_0/tioa7_1/seg13 p52/int02_0/sck3_1 4 45 p19/an09/sck2_2/seg19 p30/tiob0_1/int03_2/com7 5 44 p18/an08/sot2_2/seg20 p31/tiob1_1/sck6_1/int04_2/com6 6 43 avss p32/tiob2_1/sot6_1/int05_2/com5 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6/com4 8 41 avcc p39/adtg_2/com3 9 40 p17/an07/sin2_2/int04_1/seg21 p3a/tioa0_1/rtcco_2/subout_2/com2 10 39 p15/an05/seg23 p3b/tioa1_1/com1 11 38 p14/an04/int03_1/seg24 p3c/tioa2_1/com0 12 37 p13/an03/sck1_1/rtcco_1/subout_1/seg25 p3d/tioa3_1/seg37 13 36 p12/an02/sot1_1/seg26 p3e/tioa4_1/seg36 14 35 p11/an01/sin1_1/int02_1/wkup1/seg27 p3f/tioa5_1/seg35 15 34 p10/an00/seg28 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/seg31 p4a/tiob1_0/seg30 p4b/tiob2_0/seg29 p4c/tiob3_0/sck7_1/cec0 p4d/tiob4_0/sot7_1 p4e/tiob5_0/int06_2/sin7_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 64
document number: 002 - 05631 rev * b page 12 of 128 mb9a b 40 nb series vnc064 (top v iew) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function regist er (epfr) to select the pin. vss p81/udp0 p80/udm0 vcc p60/sin5_0/tioa2_2/int15_1/wkup3/cec1 p61/sot5_0/tiob2_2/uhconx/seg00 p62/sck5_0/adtg_3/seg01 p0f/nmix/crout_1/rtcco_0/subout_0/wkup0 p0c/sck4_0/tioa6_1 p0b/sot4_0/tiob6_1 p0a/sin4_0/int00_2 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vcc 1 48 p21/an18/sin0_0/int06_1/wkup2/seg11 p50/int00_0/sin3_1/vv4 2 47 p22/an17/sot0_0/tiob7_1/seg12 p51/int01_0/sot3_1 3 46 p23/an16/sck0_0/tioa7_1/seg13 p52/int02_0/sck3_1 4 45 p19/an09/sck2_2/seg19 p30/tiob0_1/int03_2/com7 5 44 p18/an08/sot2_2/seg20 p31/tiob1_1/sck6_1/int04_2/com6 6 43 avss p32/tiob2_1/sot6_1/int05_2/com5 7 42 avrh p33/int04_0/tiob3_1/sin6_1/adtg_6/com4 8 41 avcc p39/adtg_2/com3 9 40 p17/an07/sin2_2/int04_1/seg21 p3a/tioa0_1/rtcco_2/subout_2/com2 10 39 p15/an05/seg23 p3b/tioa1_1/com1 11 38 p14/an04/int03_1/seg24 p3c/tioa2_1/com0 12 37 p13/an03/sck1_1/rtcco_1/subout_1/seg25 p3d/tioa3_1/seg37 13 36 p12/an02/sot1_1/seg26 p3e/tioa4_1/seg36 14 35 p11/an01/sin1_1/int02_1/wkup1/seg27 p3f/tioa5_1/seg35 15 34 p10/an00/seg28 vss 16 33 vcc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c vcc p46/x0a p47/x1a initx p49/tiob0_0/seg31 p4a/tiob1_0/seg30 p4b/tiob2_0/seg29 p4c/tiob3_0/sck7_1/cec0 p4d/tiob4_0/sot7_1 p4e/tiob5_0/int06_2/sin7_1 pe0/md1 md0 pe2/x0 pe3/x1 vss qfn - 64
document number: 002 - 05631 rev * b page 13 of 128 mb9a b 40 nb series lbc112 (top view) note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. p4a md0 x0 x1 vss md1 vss vcc l vss c x0a vss p41 p45 j vcc p3f vss p40 an00 k vcc vss x1a initx p42 p48 p4b p4e p43 p49 p4d an02 vss an01 an07 an06 avss h p3b p3c p3e vss p44 p4c g p37 p38 p3a p3d an08 an05 vss an04 an03 avcc an11 f p34 p35 p36 p39 an13 an10 an09 avrh e p30 p31 p32 p33 index an17 an14 an12 vss an19 an18 d p53 p54 p55 vss an15 p56 p63 p0a vss an21 an16 c p50 p51 vss p60 p62 p0d p09 an20 b vcc vss p52 p61 p0f p0c an23 tdo/ swo p0b an22 tms/ swdio trstx vcc vss tck/ swclk vss tdi 9 10 11 a vss udp0 udm0 vcc p0e 1 2 3 4 5 6 7 8 pfbga - 112
document number: 002 - 05631 rev * b page 14 of 128 mb9a b 40 nb series fdg096 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p4b md0 x0 x1 vss l vss c x0a vss p44 an03 avcc p49 p4c p4e md1 vss vcc k vcc vss x1a initx p45 j p3d p3e vss p3f p48 an05 avss h p3a p3b p3c p4a p4d an02 vss an01 an00 an04 an08 an07 avrh g p32 p33 p39 an06 f vss vss vss e p56 p30 p31 an11 an10 an09 vss an19 an18 d p53 p54 p55 index vss an17 an16 c p50 p51 vss p60 p62 p0e p0b p0a b vcc vss p52 p61 p63 p0d p0c tdo/ swo p0f vss an22 tms/ swdio trstx vss tck/ swclk vss tdi 9 10 11 a vss udp0 udm0 vcc vss 1 2 3 4 5 6 7 8 pfbga - 96
document number: 002 - 05631 rev * b page 15 of 128 mb9a b 40 nb series 4. list of pin functions 4.1 list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relo cated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqf p - 80 bga - 96 lqfp - 64 qfn - 64 1 79 b1 1 b1 1 vcc - 2 80 c1 2 c1 2 p50 j y int00_0 sin3_1 vv4 - madata00_1 3 81 c2 3 c2 - p51 j y int01_0 sot3_1 (sda3_1) vv3 madata01_1 - - - - - 3 p 51 e l int01_0 sot3_1 (sda3_1) 4 82 b3 4 b3 - p52 j y int02_0 sck3_1 (scl3_1) vv2 madata02_1 - - - - - 4 p52 e l int02_0 sck3_1 (scl3_1) 5 83 d1 5 d1 - p53 j y sin6_0 tioa1_2 int07_2 vv1 madata03_1 6 84 d2 6 d2 - p54 j x sot6_0 (sda6_0) tiob1_2 vv0 madata04_1
document number: 002 - 05631 rev * b page 16 of 128 mb9a b 40 nb series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 l qfp - 64 qfn - 64 7 85 d3 7 d3 - p55 k u sck6_0 (scl6_0) adtg_1 seg39 madata05_1 8 86 d5 8 e1 - p56 k v int08_2 seg38 madata06_1 9 87 e1 9 e2 5 p30 k v tiob0_1 int03_2 com7 - madata07_1 10 88 e2 10 e3 6 p31 k v tiob1_1 sck6_1 (scl6_1) int04_2 com6 - madata08_1 11 89 e3 11 g1 7 p32 k v tiob2_1 sot6_1 (sda6_1) int05_2 com5 - madata09_1 12 90 e4 12 g2 8 p33 k v int04_0 tiob3_1 sin6_1 adtg_6 com4 - madata10_1 13 91 f1 - - - p34 e k tiob4_1 madata11_1 14 92 f2 - - - p35 e l tiob5_1 int08_ 1 madata12_1
document number: 002 - 05631 rev * b page 17 of 128 mb9a b 40 nb series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 15 93 f3 - - - p36 e l sin5_2 int09_1 madata13_1 - - - - f1 - vss - - - - - f2 - vss - - - - - f3 - vss - 16 94 g1 - - - p37 e l sot5_2 (sda5_2) int10_1 madata14_1 17 95 g2 - - - p38 e l sck5_2 (scl5_2) int11_1 madata15_1 18 96 f4 13 g3 9 p39 k u adtg_2 com3 19 97 g3 14 h1 10 p3a k u tioa0_1 rtcco_2 subout_2 com2 20 98 h1 15 h2 11 p3b k u tioa1_1 com1 21 99 h2 16 h3 12 p3c k u tioa2_1 com0 22 100 g4 17 j1 13 p3d k u tioa3_1 seg37 - - b2 - b2 - vss - 23 1 h3 18 j2 14 p3e k u tioa4_1 seg36 24 2 j2 19 j4 15 p3f k u tioa5_1 seg35 25 3 l1 20 l1 16 vss - 26 4 j1 - - - vcc -
document number: 002 - 05631 rev * b page 18 of 128 mb9a b 40 nb series pin no pin name i / o circuit type pin state type lqfp - 100 qfp - 100 b ga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 27 5 j4 - - - p40 e l tioa0_0 int12_1 28 6 l5 - - - p41 e l tioa1_0 int13_1 29 7 k5 - - - p42 e k tioa2_0 30 8 j5 - - - p43 e k tioa3_0 adtg_7 31 9 h5 21 l5 - p44 k u tioa4_0 seg34 mad00_1 32 10 l6 22 k5 - p45 k u tioa5_0 seg33 mad01_1 - - k2 - k2 - vss - - - j3 - j3 - vss - - - h4 - - - vss - - - - - l6 - vss - 33 11 l2 23 l2 17 c - 34 12 l 4 24 l4 - vss - 35 13 k1 25 k1 18 vcc - 36 14 l3 26 l3 19 p46 d f x0a 37 15 k3 27 k3 20 p47 d g x1a 38 16 k4 28 k4 21 initx b c 39 17 k6 29 j5 - p48 k v int14_1 sin3_2 seg32 mad02_1 40 18 j6 30 k6 22 p49 k u tiob0_0 seg31 - sot3_2 (sda3_2) mad03_1
document number: 002 - 05631 rev * b page 19 of 128 mb9a b 40 nb series pin no pin name i / o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 41 19 l7 31 j6 23 p4a k u tiob1_0 seg30 - sck3_2 (scl3_2) mad04_1 42 20 k7 32 l7 24 p4b k u tiob2_0 seg29 - mad05_1 43 21 h6 33 k7 25 p4c i * s tiob3_0 sck7_1 (scl7_1) cec0 - mad06_1 44 22 j7 34 j7 26 p4d i * k tiob4_0 sot7_1 sda7_1) - mad07_1 45 23 k8 35 k8 27 p4e i * l tiob5_0 int06_2 sin7_1 - mad08_1 46 24 k9 36 k9 28 md1 c e pe0 47 25 l8 37 l8 29 md0 g d 48 26 l9 38 l9 30 x0 a a pe2 49 27 l10 39 l10 31 x1 a b pe3 50 28 l11 40 l11 32 vss - 51 29 k11 41 k11 33 vcc - 52 30 j11 42 j11 34 p10 l w an00 seg28 53 31 j10 43 j10 35 p11 l r an01 sin1_1 int02_1 wkup1 seg27 - mad09_1
document number: 002 - 05631 rev * b page 20 of 128 mb9a b 40 nb series pin no pin name i / o circuit type pin state type lqfp - 100 qfp - 10 0 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 54 32 j8 44 j8 36 p12 l w an02 sot1_1.(sda1_1) seg26 - mad10_1 - - k10 - k10 - vss - - - j9 - j9 - vss - 55 33 h10 45 h10 37 p13 l w an03 sck1_1 (scl1_1) rtcco_1 seg25 subout_1 - mad11_1 56 34 h9 46 h9 38 p14 l n an04 int03_1 seg24 - sin0_1 mad1 2_1 57 35 h7 47 g10 39 p15 l w an05 seg23 - sot0_1 (sda0_1) mad13_1 58 36 g10 48 g9 - p16 l w an06 sck0_1 (scl0_1) seg22 mad14_1 59 37 g9 49 f10 40 p17 l n an07 sin 2_2 int04_1 seg21 - mad15_1 60 38 h11 50 h11 41 avcc - 61 39 f11 51 f11 42 avrh - 62 40 g11 52 g11 43 avss -
document number: 002 - 05631 rev * b page 21 of 128 mb9a b 40 nb series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 63 41 g8 53 f9 44 p18 l w an08 sot2_2 (sda2_2) seg20 - mad16_1 64 42 f10 54 e11 45 p19 l w an09 sck2_2 (scl2_2) seg19 - mad17_1 - - h8 - - - vss - 65 43 f9 55 e10 - p1a l n an10 sin4_1 int05_1 seg18 mad18_1 66 44 e11 56 e 9 - p1b l w an11 sot4_1 (sda4_1) seg17 mad19_1 67 45 e10 - - - p1c l w an12 sck4_1 (scl4_1) seg16 mad20_ 1 68 46 f8 - - - p1d l w an13 cts4_1 seg15 mad21_1 69 47 e9 - - - p1e l w an14 rts4_1 seg14 mad22_1 70 48 d11 - - - p1f f m an15 adtg_5 mad23_1
document number: 002 - 05631 rev * b page 22 of 128 mb9a b 40 nb series pin n o pin name i / o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 - - b10 - b10 - vss - - - c9 - c9 - vss - - - - - d11 - vss - 71 49 d10 57 d10 46 p23 l w an16 sck0_0 (scl0_0) tioa7_1 seg13 72 50 e8 58 d9 47 p22 l w an17 sot0_0 (sda0_0) tiob7_1 seg12 73 51 c11 59 c11 48 p21 l r an18 sin0_0 int06_1 wkup2 seg11 74 52 c10 60 c10 - p20 l n an19 int05_0 crout_0 seg10 mad24_1 75 53 a11 - a11 - vss - 76 54 a10 - - - vcc - 77 55 a9 61 a 10 49 p00 e j trstx - mcsx7_1 78 56 b9 62 b9 50 p01 e j tck swclk 79 57 b11 63 b11 51 p02 e j tdi - mcsx6_1 80 58 a8 64 a9 52 p03 e j tms swdio 81 59 b8 65 b8 53 p04 e j tdo swo
document number: 002 - 05631 rev * b page 23 of 128 mb9a b 40 nb series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 82 60 c8 - - - p05 l q an20 traced0 tioa5_2 sin4_2 int00_1 seg09 mcsx5_1 - - d8 - - - vss - 83 61 d9 - - - p06 l q an21 traced1 tiob5_2 sot4_2 (sda4_2) int01_1 seg08 mcsx4_1 84 62 a7 66 a8 - p07 l p an22 adtg_0 seg07 mclkout_1 - - traced2 sck4_2 (scl4_2) - - - - a7 - vss - 85 63 b7 - - - p08 l p an23 traced3 tioa0_2 cts4_2 seg06 mcsx3_1 86 64 c7 - - - p09 k o traceclk tiob0_2 rts4_2 seg05 mcsx2_1 87 65 d7 67 c8 54 p0a i * l sin4_0 int00_2 - mcsx1_1
document number: 002 - 05631 rev * b page 24 of 128 mb9a b 40 nb series pi n no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 88 66 a6 68 c7 55 p0b i * k sot4_0 (sda4_0) tiob6_1 - mcsx0_1 89 67 b6 69 b7 56 p0c i * k sck4_0 (scl4_0) ti oa6_1 - male_1 - - d4 - - - vss - - - c3 - c3 - vss - 90 68 c6 70 b6 - p0d k u rts4_0 tioa3_2 seg04 mdqm0_1 91 69 a5 71 c6 - p0e k u cts4_0 tiob3_2 seg03 mdqm1_1 - - - - a5 - vss - 92 70 b5 72 a6 57 p0f e i nmix crout_1 rtcco_0 subout_0 wkup0 93 71 d6 73 b5 - p63 k v int03_0 seg02 mwex_1 94 72 c5 74 c5 58 p62 k u sck5_0 (scl5_0) adt g_3 seg01 - moex_1 95 73 b4 75 b4 59 p61 k u sot5_0 (sda5_0) tiob2_2 uhconx seg00
document number: 002 - 05631 rev * b page 25 of 128 mb9a b 40 nb series pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp - 64 qfn - 64 96 74 c4 76 c4 60 p60 i * t sin5_0 tioa2_2 int15_1 wkup3 cec1 - mrdy_1 97 75 a4 77 a4 61 vcc - 98 76 a3 78 a3 62 p80 h h udm0 99 77 a2 79 a2 63 p81 h h udp0 100 78 a1 80 a1 64 vss - - *: 5 v tolerant i/o
document number: 002 - 05631 rev * b page 26 of 128 mb9a b 40 nb series 4.2 list of pin functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 adc adtg_0 a/d converter external trigger input pin 84 62 a7 66 a8 - adtg_1 7 85 d3 7 d 3 - adtg_2 18 96 f4 13 g3 9 adtg_3 94 72 c5 74 c5 58 adtg_4 - - - - - - adtg_5 70 48 d11 - - - adtg_6 12 90 e4 12 g2 8 adtg_7 30 8 j5 - - - adtg_8 - - - - - - an00 a/d converter analog input pin . anxx describes adc ch.xx . 52 30 j11 4 2 j11 34 an01 53 31 j10 43 j10 35 an02 54 32 j8 44 j8 36 an03 55 33 h10 45 h10 37 an04 56 34 h9 46 h9 38 an05 57 35 h7 47 g10 39 an06 58 36 g10 48 g9 - an07 59 37 g9 49 f10 40 an08 63 41 g8 53 f9 44 an09 64 42 f10 54 e11 45 an1 0 65 43 f9 55 e10 - an11 66 44 e11 56 e9 - an12 67 45 e10 - - - an13 68 46 f8 - - - an14 69 47 e9 - - - an15 70 48 d11 - - - an16 71 49 d10 57 d10 46 an17 72 50 e8 58 d9 47 an18 73 51 c11 59 c11 48 an19 74 52 c10 60 c10 - an20 82 60 c8 - - - an21 83 61 d9 - - - an22 84 62 a7 66 a8 - an23 85 63 b7 - - -
document number: 002 - 05631 rev * b page 27 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 base timer 0 tioa0_0 base timer ch.0 tioa pin 27 5 j4 - - - tioa0_1 19 97 g3 14 h1 10 tioa0_2 85 63 b7 - - - tiob0_0 base timer ch.0 tiob pin 40 18 j6 30 k6 22 tiob0_1 9 87 e1 9 e2 5 tiob0_2 86 64 c7 - - - base timer 1 tioa1_0 base timer ch.1 tioa pin 28 6 l5 - - - tioa1_1 20 98 h1 15 h2 11 tioa1_2 5 83 d1 5 d1 - tiob1_0 base timer ch.1 tiob pin 41 19 l7 31 j6 23 tiob1_1 10 88 e2 10 e3 6 tiob1_2 6 84 d2 6 d2 - base timer 2 tioa2_0 base timer ch.2 tioa pin 29 7 k5 - - - tioa2_1 21 99 h2 16 h3 12 tioa2_2 96 74 c4 76 c4 60 tiob 2_0 base timer ch.2 tiob pin 42 20 k7 32 l7 24 tiob2_1 11 89 e3 11 g1 7 tiob2_2 95 73 b4 75 b4 59 base timer 3 tioa3_0 base timer ch.3 tioa pin 30 8 j5 - - - tioa3_1 22 100 g4 17 j1 13 tioa3_2 90 68 c6 70 b6 - tiob3_0 base timer ch.3 tiob pi n 43 21 h6 33 k7 25 tiob3_1 12 90 e4 12 g2 8 tiob3_2 91 69 a5 71 c6 - base timer 4 tioa4_0 base timer ch.4 tioa pin 31 9 h5 21 l5 - tioa4_1 23 1 h3 18 j2 14 tioa4_2 - - - - - - tiob4_0 base timer ch.4 tiob pin 44 22 j7 34 j7 26 tiob4_1 13 91 f1 - - - tiob4_2 - - - - - - base timer 5 tioa5_0 base timer ch.5 tioa pin 32 10 l6 22 k5 - tioa5_1 24 2 j2 19 j4 15 tioa5_2 82 60 c8 - - - tiob5_0 base timer ch.5 tiob pin 45 23 k8 35 k8 27 tiob5_1 14 92 f2 - - - tiob5_2 83 61 d9 - - - base timer 6 tioa6_1 base timer ch.6 tioa pin 89 67 b6 69 b7 56 tiob6_1 base timer ch.6 tiob pin 88 66 a6 68 c7 55 base timer 7 tioa7_0 base timer ch.7 tioa pin - - - - - - tioa7_1 71 49 d10 57 d10 46 tioa7_2 - - - - - - tiob7_0 base timer c h.7 tiob pin - - - - - - tiob7_1 72 50 e8 58 d9 47 tiob7_2 - - - - - -
document number: 002 - 05631 rev * b page 28 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 debugger swclk serial wire debug interface clock input pin 78 56 b9 62 b9 50 swdio serial wire debug interface data input / output pin 80 58 a8 64 a9 52 swo serial wire viewer output pin 81 59 b8 65 b8 53 tck jtag test clock input pin 78 56 b9 62 b9 50 tdi jtag test data input pin 79 57 b11 63 b11 51 tdo jtag de bug data output pin 81 59 b8 65 b8 53 tms jtag test mode state input/output pin 80 58 a8 64 a9 52 tracecl k trace clk output pin of etm 86 64 c7 - - - traced0 trace data output pin s of etm 82 60 c8 - - - traced1 83 61 d9 - - - traced2 84 62 a7 - - - traced3 85 63 b7 - - - trstx jtag test reset input pin 77 55 a9 61 a10 49 external bus mad00 _1 external bus interface address bus 31 9 h5 21 l5 - mad01 _1 32 10 l6 22 k5 - mad02 _1 39 17 k6 29 j5 - mad03 _1 40 18 j6 30 k6 - mad04 _1 41 1 9 l7 31 j6 - mad05 _1 42 20 k7 32 l7 - mad06 _1 43 21 h6 33 k7 - mad07 _1 44 22 j7 34 j7 - mad08 _1 45 23 k8 35 k8 - mad09 _1 53 31 j10 43 j10 - mad10 _1 54 32 j8 44 j8 - mad11 _1 55 33 h10 45 h10 - mad12 _1 56 34 h9 46 h9 - mad13 _1 57 3 5 h7 47 g10 - mad14 _1 58 36 g10 48 g9 - mad15_1 59 37 g9 49 f10 - mad16 _1 63 41 g8 53 f9 - mad17 _1 64 42 f10 54 e11 - mad18 _1 65 43 f9 55 e10 - mad19 _1 66 44 e11 56 e9 - mad20 _1 67 45 e10 - - - mad21 _1 68 46 f8 - - - mad2 2_1 69 4 7 e9 - - - mad23 _1 70 48 d11 - - - mad24 _1 74 52 c10 60 c10 -
document number: 002 - 05631 rev * b page 29 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 external bus mcsx0 _1 external bus interface chip select output pin 88 66 a6 6 8 c7 - mcsx1 _1 87 65 d7 67 c8 - mcsx2 _1 86 64 c7 - - - mcsx3 _1 85 63 b7 - - - mcsx4 _1 83 61 d9 - - - mcsx5 _1 82 60 c8 - - - mcsx6 _1 79 57 b11 63 b11 - mcsx7 _1 77 55 a9 61 a10 - mdqm0 _1 external bus interface byte mask signal output p in 90 68 c6 70 b6 - mdqm1 _1 91 69 a5 71 c6 - moex _1 external bus interface read enable signal for sram 94 72 c5 74 c5 - mwex _1 external bus interface write enable signal for sram 93 71 d6 73 b5 - m a data0 0_1 external bus interface data bus 2 80 c1 2 c1 - m a data0 1_1 3 81 c2 3 c2 - m a data0 2_1 4 82 b3 4 b3 - m a data0 3_1 5 83 d1 5 d1 - m a data0 4_1 6 84 d2 6 d2 - m a data0 5_1 7 85 d3 7 d3 - m a data0 6_1 8 86 d5 8 e1 - m a data0 7_1 9 87 e1 9 e2 - m a data0 8_1 10 88 e2 10 e3 - m a data0 9_1 1 1 89 e3 11 g1 - m a data 10_1 12 90 e4 12 g2 - m a data 11_1 13 91 f1 - - - m a data 12_1 14 92 f2 - - - m a data 13_1 15 93 f3 - - - m a data 14_1 16 94 g1 - - - m a data 15_1 17 95 g2 - - - male_1 address latch enable signal for multiplex 89 67 b6 69 b 7 - mrdy_1 external bus rdy input signal 96 74 c4 76 c4 - mclkout_1 external bus clock output pin 84 62 a7 66 a8 -
document number: 002 - 05631 rev * b page 30 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 external interrupt int00_ 0 external interrupt request 00 input pin 2 80 c1 2 c1 2 int00_1 82 60 c8 - - - int00_2 87 65 d7 67 c8 54 int01_0 external interrupt request 0 1 input pin 3 81 c2 3 c2 3 int01_1 83 61 d9 - - - int02_0 external interrupt request 0 2 input pin 4 8 2 b3 4 b3 4 int02_1 53 31 j10 43 j10 35 int03_0 external interrupt request 0 3 input pin 93 71 d6 73 b5 - int03_1 56 34 h9 46 h9 38 int03_2 9 87 e1 9 e2 5 int04_0 external interrupt request 04 input pin 12 90 e4 12 g2 8 int04_1 59 37 g9 49 f 10 40 int04_2 10 88 e2 10 e3 6 int05_0 external interrupt request 0 5 input pin 74 52 c10 60 c10 - int05_1 65 43 f9 55 e10 - int05_2 11 89 e3 11 g1 7 int06_1 external interrupt request 0 6 input pin 73 51 c11 59 c11 48 int06_2 45 23 k8 35 k8 27 int07_2 external interrupt request 0 7 input pin 5 83 d1 5 d1 - int08_1 external interrupt request 0 8 input pin 14 92 f2 - - - int08_2 8 86 d5 8 e1 - int09_1 external interrupt request 0 9 input pin 15 93 f3 - - - int10_1 external interrupt req uest 10 input pin 16 94 g1 - - - int11_1 external interrupt request 11 input pin 17 95 g2 - - - int12_1 external interrupt request 12 input pin 27 5 j4 - - - int13_1 external interrupt request 13 input pin 28 6 l5 - - - int14_1 external interrupt r equest 14 input pin 39 17 k6 29 j5 - int15_1 external interrupt request 15 input pin 96 74 c4 76 c4 60 nmix non - maskable interrupt input pin 92 70 b5 72 a6 57
document number: 002 - 05631 rev * b page 31 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bg a - 96 lqfp / qfn - 64 gpio p00 general - purpose i/o port 0 77 55 a9 61 a10 49 p01 78 56 b9 62 b9 50 p02 79 57 b11 63 b11 51 p03 80 58 a8 64 a9 52 p04 81 59 b8 65 b8 53 p05 82 60 c8 - - - p06 83 61 d9 - - - p07 84 62 a7 66 a8 - p08 85 63 b7 - - - p09 86 64 c7 - - - p0a 87 65 d7 67 c8 54 p0b 88 66 a6 68 c7 55 p0c 89 67 b6 69 b7 56 p0d 90 68 c6 70 b6 - p0e 91 69 a5 71 c6 - p0f 92 70 b5 72 a6 57 p10 general - purpose i/o port 1 52 30 j11 42 j11 34 p11 53 31 j10 43 j10 35 p12 54 32 j8 44 j8 36 p13 55 33 h10 45 h10 37 p14 56 34 h9 46 h9 38 p15 57 35 h7 47 g10 39 p16 58 36 g10 48 g9 - p17 59 37 g9 49 f10 40 p18 63 41 g8 53 f9 44 p19 64 42 f10 54 e11 45 p1a 65 43 f9 55 e10 - p1b 66 44 e11 56 e 9 - p1c 67 45 e10 - - - p1d 68 46 f8 - - - p1e 69 47 e9 - - - p1f 70 48 d11 - - - p20 general - purpose i/o port 2 74 52 c10 60 c10 - p21 73 51 c11 59 c11 48 p22 72 50 e8 58 d9 47 p23 71 49 d10 57 d10 46
document number: 002 - 05631 rev * b page 32 of 128 mb9a b 40 nb series pin function pin name functi on description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 gpio p30 general - purpose i/o port 3 9 87 e1 9 e2 5 p31 10 88 e2 10 e3 6 p32 11 89 e3 11 g1 7 p33 12 90 e4 12 g2 8 p34 13 91 f1 - - - p35 14 92 f2 - - - p36 15 93 f3 - - - p37 16 94 g1 - - - p38 17 95 g2 - - - p39 18 96 f4 13 g3 9 p3a 19 97 g3 14 h1 10 p3b 20 98 h1 15 h2 11 p3c 21 99 h2 16 h3 12 p3d 22 100 g4 17 j1 13 p3e 23 1 h3 18 j2 14 p3f 24 2 j2 19 j4 15 p40 g eneral - purpose i/o port 4 27 5 j4 - - - p41 28 6 l5 - - - p42 29 7 k5 - - - p43 30 8 j5 - - - p44 31 9 h5 21 l5 - p45 32 10 l6 22 k5 - p46 36 14 l3 26 l3 19 p47 37 15 k3 27 k3 20 p48 39 17 k6 29 j5 - p49 40 18 j6 30 k6 22 p4a 41 19 l7 31 j6 23 p4b 42 20 k7 32 l7 24 p4c 43 21 h6 33 k7 25 p4d 44 22 j7 34 j7 26 p4e 45 23 k8 35 k8 27 p50 general - purpose i/o port 5 2 80 c1 2 c1 2 p51 3 81 c2 3 c2 3 p52 4 82 b3 4 b3 4 p53 5 83 d1 5 d1 - p54 6 84 d2 6 d2 - p55 7 85 d3 7 d3 - p56 8 86 d5 8 e1 - p60 general - purpose i/o port 6 96 74 c4 76 c4 60 p61 95 73 b4 75 b4 59 p62 94 72 c5 74 c5 58 p6 3 93 71 d6 73 b5 - p80 general - purpose i/o port 8 98 76 a3 78 a3 62 p81 99 77 a2 79 a2 63 pe0 general - purpose i/o port e 46 24 k9 36 k9 28 pe2 48 26 l9 38 l9 30 pe3 49 27 l10 39 l10 31
document number: 002 - 05631 rev * b page 33 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 multi - function serial0 sin0_0 multi - function serial i nterface ch.0 input pin 73 51 c11 59 c11 48 sin0_1 56 34 h9 46 h9 - sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda0 when it is used in an i 2 c (operation mode 4). 72 50 e8 58 d9 47 sot0_1 (sda0_1) 57 35 h7 47 g10 - sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2 ) and as scl0 when it is used in an i 2 c (operation mode 4). 71 49 d10 57 d10 46 sck0_1 (scl0_1) 58 36 g10 48 g9 - multi - function serial1 sin1_1 multi - function serial interface ch.1 input pin 53 31 j10 43 j10 35 sot1_1 (sda1_1) multi - function serial interface ch.1 output pin. th is pin operates as sot1 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda1 when it is used in an i 2 c (operation mode 4). 54 32 j8 44 j8 36 sck1_1 (scl1_1) multi - function serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a uart/csio (operation modes 0 to 2) and as scl1 when it is used in an i 2 c (operation mode 4). 55 33 h10 45 h10 37
document number: 002 - 05631 rev * b page 34 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 6 4 multi - function serial 2 sin2_ 2 multi - function serial interface ch.2 input pin 59 37 g9 49 f10 40 sot2_ 2 (sda2_ 2 ) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda2 when it is u sed in an i 2 c (operation mode 4). 63 41 g8 53 f9 44 sck2_ 2 (scl2_ 2 ) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a uart/csio (operation modes 0 to 2) and as scl2 when it is used in an i 2 c (operation mod e 4). 64 42 f10 54 e11 45 multi - function serial 3 sin3_ 1 multi - function serial interface ch.3 input pin 2 80 c1 2 c1 2 sin3_ 2 39 17 k6 29 j5 - sot3_ 1 (sda3_ 1 ) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio (operation modes 0 to 2) and as sda3 when it is used in an i 2 c (operation mode 4). 3 81 c2 3 c2 3 sot3_ 2 (sda3_ 2 ) 40 18 j6 30 k6 - sck3_ 1 (scl3_ 1 ) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a uart/csio (operation modes 0 to 2 ) and as scl3 when it is used in an i 2 c (operation mode 4). 4 82 b3 4 b3 4 sck3_ 2 (scl3_ 2 ) 41 19 l7 31 j6 -
document number: 002 - 05631 rev * b page 35 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqf p / qfn - 64 multi - function serial 4 sin4_0 multi - function serial interface ch.4 input pin 87 65 d7 67 c8 54 sin4_1 65 43 f9 55 e10 - sin4_2 82 60 c8 - - - sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 wh en it is used in a uart/csio (operation modes 0 to 2 ) and as sda4 when it is used in an i 2 c (operation mode 4). 88 66 a6 68 c7 55 sot4_1 (sda4_1) 66 44 e11 56 e9 - sot4_2 (sda4_2) 83 61 d9 - - - sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a uart/csio (operation modes 0 to 2 ) and as scl4 when it is used in an i 2 c (operation mode 4). 89 67 b6 69 b7 56 sck4_1 (scl4_1) 67 45 e10 - - - sck4_2 (scl4_2) 84 62 a7 - - - rts4_0 multi - function serial interface ch.4 rts output pin 90 68 c6 70 b6 - rts4_1 69 47 e9 - - - rts4_2 86 64 c7 - - - cts4_0 multi - function serial interface ch.4 cts input pin 91 69 a5 71 c6 - cts4_1 68 46 f8 - - - cts4_2 85 63 b7 - - - multi - functio n serial 5 sin5_0 multi - function serial interface ch.5 input pin 96 74 c4 76 c4 60 sin5_2 15 93 f3 - - - sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda5 when it is used in an i 2 c (operation mode 4). 95 73 b4 75 b4 59 sot5_2 (sda5_2) 16 94 g1 - - - sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a uart/csio (operation modes 0 to 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 94 72 c5 74 c5 58 sck5_2 (scl5_2) 17 95 g2 - - -
document number: 002 - 05631 rev * b page 36 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 multi - function serial 6 si n6_0 multi - function serial interface ch.6 input pin 5 83 d1 5 d1 - sin6_1 12 90 e4 12 g2 8 sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda6 w hen it is used in an i 2 c (operation mode 4). 6 84 d2 6 d2 - sot6_1 (sda6_1) 11 89 e3 11 g1 7 sck6_0 (scl6_0) multi - function serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a uart/csio (operation modes 0 to 2 ) and as s cl6 when it is used in an i 2 c (operation mode 4). 7 85 d3 7 d3 - sck6_1 (scl6_1) 10 88 e2 10 e3 6 multi - function serial 7 sin7_ 1 multi - function serial interface ch.7 input pin 45 23 k8 35 k8 27 sot7_ 1 (sda7_ 1 ) multi - function serial interface ch.7 ou tput pin. this pin operates as sot7 when it is used in a uart/csio (operation modes 0 to 2 ) and as sda7 when it is used in an i 2 c (operation mode 4). 44 22 j7 34 j7 26 sck7_ 1 (scl7_ 1 ) multi - function serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a uart/csio (operation modes 0 to 2 ) and as scl7 when it is used in an i 2 c (operation mode 4). 43 21 h6 33 k7 25
document number: 002 - 05631 rev * b page 37 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 usb udm0 usb device /host d C pin 98 76 a3 78 a3 62 udp0 usb device /host d + pin 99 77 a2 79 a2 63 uhconx usb external pull - up control pin 95 73 b4 75 b4 59 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 92 70 b5 72 a6 57 rtcco_1 55 33 h10 45 h10 37 rtcco_2 19 97 g3 14 h1 10 subout_0 sub clock output pin 92 70 b5 72 a6 57 subout_1 55 33 h10 45 h10 37 subout_2 19 97 g3 14 h1 10 low - power consumption mode wkup0 deep standby mode return signal input pin 0 92 70 b5 72 a6 57 wkup1 deep standby mode return signal input pin 1 53 31 j10 43 j10 35 wkup2 deep standby mode return signal input pin 2 73 51 c11 59 c11 48 wkup3 deep standby mode return signal input pin 3 96 74 c4 76 c4 60 hdmi - cec/ remote control reception c ec0 hdmi - cec/remote control reception ch.0 input/output pin 43 21 h6 33 k7 25 cec1 hdmi - cec/remote control reception ch.1 input/output pin 96 74 c4 76 c4 60 lcdc vv0 lcd drive power supply pin 6 84 d2 6 d2 - vv1 5 83 d1 5 d1 - vv2 4 82 b3 4 b3 - vv3 3 81 c2 3 c2 - vv4 2 80 c1 2 c1 2 com0 lcd common output pin 21 99 h2 16 h3 12 com1 20 98 h1 15 h2 11 com2 19 97 g3 14 h1 10 com3 18 96 f4 13 g3 9 com4 12 90 e4 12 g2 8 com5 11 89 e3 11 g1 7 com6 10 88 e2 10 e3 6 com7 9 87 e 1 9 e2 5
document number: 002 - 05631 rev * b page 38 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 lcdc seg00 lcd segment output pin 95 73 b4 75 b4 59 seg01 94 72 c5 74 c5 58 seg02 93 71 d6 73 b5 - seg03 91 69 a5 71 c6 - s eg04 90 68 c6 70 b6 - seg05 86 64 c7 - - - seg06 85 63 b7 - - - seg07 84 62 a7 66 a8 - seg08 83 61 d9 - - - seg09 82 60 c8 - - - seg10 74 52 c10 60 c10 - seg11 73 51 c11 59 c11 48 seg12 72 50 e8 58 d9 47 seg13 71 49 d10 57 d10 4 6 seg14 69 47 e9 - - - seg15 68 46 f8 - - - seg16 67 45 e10 - - - seg17 66 44 e11 56 e9 - seg18 65 43 f9 55 e10 - seg19 64 42 f10 54 e11 45 seg20 63 41 g8 53 f9 44 seg21 59 37 g9 49 f10 40 seg22 58 36 g10 48 g9 - seg23 57 35 h 7 47 g10 39 seg24 56 34 h9 46 h9 38 seg25 55 33 h10 45 h10 37 seg26 54 32 j8 44 j8 36 seg27 53 31 j10 43 j10 35 seg28 52 30 j11 42 j11 34 seg29 42 20 k7 32 l7 24 seg30 41 19 l7 31 j6 23 seg31 40 18 j6 30 k6 22 seg32 39 17 k6 29 j 5 - seg33 32 10 l6 22 k5 - seg34 31 9 h5 21 l5 - seg35 24 2 j2 19 j4 15 seg36 23 1 h3 18 j2 14 seg37 22 100 g4 17 j1 13 seg38 8 86 d5 8 e1 - seg39 7 85 d3 7 d3 -
document number: 002 - 05631 rev * b page 39 of 128 mb9a b 40 nb series pin function pin name function description pin no lqfp - 100 qfp - 10 0 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 reset initx external reset input pin. a reset is valid when initx=l. 38 16 k4 28 k4 21 mode md0 mode 0 pin. during normal operation, md0=l must be input. during serial programming to f lash memory, md0=h must be input . 47 25 l8 37 l8 29 md1 mode 1 pin. during serial programming to f lash memory, md1=l must be input. 46 24 k9 36 k9 28 power vcc power supply pin 1 79 b1 1 b1 1 26 4 j1 - - - 35 13 k1 25 k1 18 51 29 k11 41 k11 33 76 54 a10 - - - 97 75 a4 77 a4 61 gnd vss gnd pin - - - - f1 - - - - - f2 - - - - - f3 - - - b2 - b2 - 25 3 l1 20 l1 16 - - k2 - k2 - - - j3 - j3 - - - h4 - - - - - - - l6 - 34 12 l4 24 l4 - 50 28 l11 40 l11 32 - - k10 - k10 - - - j9 - j9 - - - h8 - - - - - b10 - b10 - - - c9 - c9 - - - - - d11 - 75 53 a11 - a11 - - - d8 - - - - - - - a7 - - - d4 - - - - - c3 - c3 - - - - - a5 - 100 78 a1 80 a1 64
document number: 002 - 05631 rev * b page 40 of 128 mb9a b 40 nb series pin function pin name function desc ription pin no lqfp - 100 qfp - 100 bga - 112 lqfp - 80 bga - 96 lqfp / qfn - 64 clock x0 main clock (oscillation) input pin 48 26 l9 38 l9 30 x0a sub clock (oscillation) input pin 36 14 l3 26 l3 19 x1 main clock (oscillation) i/o pin 49 27 l10 39 l10 31 x1a sub clock (oscillation) i/o pin 37 15 k3 27 k3 20 crout _0 built - in high - speed cr - osc clock output port 74 52 c10 60 c10 - crout _1 92 70 b5 72 a6 57 adc power avcc a/d converter analog power supply pin 60 38 h11 50 h11 41 avrh a/d converter analog reference voltage input pin 61 39 f11 51 f11 42 adc gnd avss a/d converter gnd pin 62 40 g11 52 g11 43 c pin c power supply stabilization capacity pin 33 11 l2 23 l2 17 note: ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2 001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 05631 rev * b page 41 of 128 mb9a b 40 nb series 5. i /o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedb ack resistor: approximately 1 m ? with standby mode control ? when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor digital output dig ital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control
document number: 002 - 05631 rev * b page 42 of 128 mb9a b 40 nb series type circuit remarks b ? cmos level h ysteresis input ? pull - up resistor: approximately 33 k c ? open drain output ? cmos level hysteresis input pull - up resistor digital in put digital input digital out put n-ch
document number: 002 - 05631 rev * b page 43 of 128 mb9a b 40 nb series type circuit remarks d it is possible to select the sub oscillation / gpio function when the sub oscillation i s selected. ? oscillation feedback resistor: approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor d igital output digital output pull - up resistor control digital input standby mode c ontrol clock input standby mode c ontrol digital input standby mode c ontrol digital output digital output pull - up resistor control
document number: 002 - 05631 rev * b page 44 of 128 mb9a b 40 nb series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digi tal output p - ch transistor is always off f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 05631 rev * b page 45 of 128 mb9a b 40 nb series type circuit remarks g cmos level hysteresis input h it is possible to select the usb i/o / gpio function. when the usb i/ o is selected. ? full - speed, low - speed control when the gpio is selected. ? cmos level output ? cmos level hysteresis input ? with standby mode control i ? cmos level output ? cmos level hysteresis input ? 5 v tolerant ? with pull - up resistor contr ol ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? available to control pzr registers. ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off mode input gpio di gital output gpio digital input/output direction gpio digital input gpio digital input circuit control udp output usb full - speed/low - speed control udp input differential input usb/gpio select udm input udm output usb digital inp ut/output direction gpio digital output gpio digital input/output direction gpio digital input gpio digital input circuit control digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r udp0/p81 udm0/p80 di f ferential
document number: 002 - 05631 rev * b page 46 of 128 mb9a b 40 nb series type circuit remarks j ? cmos level output ? cmos level h ysteresis input ? with input control ? lcd - vv input/output ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always o ff k ? cmos level output ? cmos level hysteresis input ? with input control ? lcd output ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digi tal output p - ch transistor is always off digital output digital output pull - up resistor cont rol digital input standby mode c ontrol lcd vv input / output lcd vv control digital output digital output pull - up resistor control digital input standby mode c ontrol lcd out put lcd control p-ch p-ch n-ch r
document number: 002 - 05631 rev * b page 47 of 128 mb9a b 40 nb series type circuit remarks l ? cmos level output ? cmos level hysteresis input ? with input control ? lcd output ? with pull - up resistor control ? with standby mode control ? pull - up resistor: approximately 33 k ? ioh= - 4 ma, iol= 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off digital output digital output pull - up resistor cont rol digital input standby mode c ontrol analog input input control lcd out put lcd control p-ch p-ch n-ch r
document number: 002 - 05631 rev * b page 48 of 128 mb9a b 40 nb series 6. handling precautions any semiconductor device has inherently a certain rate of failure. the possibility of failure is greatly affected by the cond itions in which they a re used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design t his section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are w arranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect t o uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. proces s ing and protection of pins these precautions m ust be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is like ly to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or o ther output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pin s with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type an d n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution : the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulati ons and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products.
document number: 002 - 05631 rev * b page 49 of 128 mb9a b 40 nb series fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from suc h failures by incorporating safety design measures into your facility and equipment such as redundancy, fire pro tection, and prevention of over - current levels and other abnormal operating conditions. precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equip ment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause p hysical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to cons ult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval . 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in eit her case, for heat resistance during soldering, you should only mount under cypress's recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages o nto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (w ave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket conta cts and ic leads be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrow er pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress inc. recommends the solder reflow method, and has established a ranking o f mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions.
document number: 002 - 05631 rev * b page 50 of 128 mb9a b 40 nb series lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moistu re to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry pack age that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress inc. packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bag s for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. conditi on: 125 c /24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an appa ratus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high r esistance (on the level of 1 m). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies.
document number: 002 - 05631 rev * b page 51 of 128 mb9a b 40 nb series 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable perform ance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may le ad to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments in volving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, t here is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 05631 rev * b page 52 of 128 mb9a b 40 nb series 7. handling devices power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagn etic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this devi ce at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin and gnd pin , between avcc pin and avss pin near this device. stabilizing supply voltage a malfunctio n may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the flu ctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctu ation on switching the power supply. crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to gro und are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation o f your using crystal oscillator by your mount board. sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillato r to stabilize the oscillation. surface mount type size: more than 3.2 mm 1.5 mm load capacitance: approximately 6 pf to 7 pf lead type load capacitance: approximately 6 pf to 7 pf using an external clock when using an external clock as an input of t he main clock, set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using an external clock as an input of the sub clock, set x0 a/ x1 a to the external clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. example of using an external clock device x0 ( x0a ) x1(pe3), x1a (p47) can be used as general - purpose i/o ports. set as external clock input
document number: 002 - 05631 rev * b page 53 of 128 mb9a b 40 nb series handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is alway s disabled. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regul ator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to ther mal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditio ns to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7f wou ld be recommended for this series. mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switchi ng to test mode due to noise. notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, connect avcc = vcc and avss = vss. turning on : vcc avcc avrh turning off : avrh avcc vcc serial communi cation there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detectio n such as by applying a checksum of data at the end. if an error is detected , retransmit the data. differences in features among the products with different memory sizes and between flash memory products and mask products the electric characteristics inclu ding power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask products are different because chip layout and memory structures are dif ferent. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics . pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i / o. device c vss c s gnd
document number: 002 - 05631 rev * b page 54 of 128 mb9a b 40 nb series 8. block diagram *1: for the mb9afb41 l b /m b, mb9afb42 l b /m b, and mb9afb44 l b /m b , etm is not available. *2: for the mb9afb41 l b, mb9afb42 l b and mb9afb44 l b , the external bus i nterface is not available. and the multi - function serial interface does not support hardware flow control in th ese products. 9. memory size see memory size in product lineup to confirm the memory size. c o r t e x - m 3 f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . w a t c h c o u n t e r u n i t 0 c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i p o w e r - o n r e s e t s r a m 0 8 / 1 6 k b y t e s r a m 1 8 / 1 6 k b y t e i d s y s n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r u n i t 1 t r s t x , t c k , t d i , t m s t r a c e d x , t r a c e c l k a v c c , a v s s , a v r h a n x x t i o a x t i o b x c t d o s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p e x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a d t g x r t s 4 c t s 4 m a d x m a d a t a x m c s x x , m o e x , m w e x , m a l e , m r d y , m c l k o u t , m d q m x o n - c h i p f l a s h 6 4 + 3 2 k b y t e / 1 2 8 + 3 2 k b y t e / 2 5 6 + 3 2 k b y t e u d p 0 / u d m 0 u h c o n x m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 t o c h . 7 ) h w f l o w c o n t r o l ( c h . 4 ) * 2 e x t e r n a l b u s i / f * 2 g p i o p i n - f u n c t i o n - c t r l l v d u s b 2 . 0 ( h o s t / d e v i c e ) p h y t p i u * 1 r o m t a b l e e t m * 1 s w j - d p c e c 0 , c e c 1 v v x c o m x , s e g x l v d c t r l b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . h d m i - c e c / r e m o t e r e c i v e r c o n t r o l r e a l - t i m e c l o c k l c d c r t c c o , s u b o u t u s b c l o c k c t r l p l l d e e p s t a n d b y c t r l w k u p x c l k x 0 x 1 x 0 a x 1 a m a i n o s c p l l s u b o s c c r 4 m h z c r 1 0 0 k h z c r o u t s o u r c e c l o c k a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) m u l t i - l a y e r a h b ( m a x 4 0 m h z ) a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z )
document number: 002 - 05631 rev * b page 55 of 128 mb9a b 40 nb series 10. memory map memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_1000 0xe000_0000 0x4006_0000 dmac 0x4005_0000 reserved 0x4004_0000 usb ch.0 0x4003_f000 ext-bus i/f 0x4003_c000 reserved 0x4003_b000 rtc 0x4003_a000 watch counter 0x7000_0000 0x4003_9000 crc 0x4003_8000 mfs 0x6000_0000 0x4003_7000 reserved 0x4003_6000 usb clock ctrl 0x4003_5000 lvd/ds mode 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 gpio 0x4003_2000 lcdc 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x4002_f000 reserved 0x2400_0000 0x4002_e000 cr trim 0x2200_0000 0x4002_8000 0x4002_7000 a/dc 0x4002_6000 reserved 0x2008_0000 0x4002_5000 base timer 0x2000_0000 sram1 0x1fff_0000 sram0 0x0020_8000 reserved 0x0020_0000 flash(work area) 0x0010_4000 reserved 0x0010_0000 security/cr trim 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x4001_2000 sw wdt 0x0000_0000 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved reserved reserved reserved cortex-m3 private peripherals reserved reserved external device area see the next page " l memory map (2)" for the memory size details. hdmi-cec/ remote control receiver reserved peripherals reserved 32mbytes bit band alias reserved reserved 32mbytes bit band alias flash(main area)
document number: 002 - 05631 rev * b page 56 of 128 mb9a b 40 nb series memory map (2) r efer to the programming manual for the detail of flash main area. mb9ab40n/a40n/340n/140n/150r,mb9b520m/320m/120m series flash programming manual mb9afb44lb/mb/nb mb9afb42lb/mb/nb mb9afb41lb/mb/nb 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_e000 0x1fff_e000 0x1fff_c000 0x0020_8000 0x0020_8000 0x0020_8000 0x0020_0000 0x0020_0000 0x0020_0000 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_2000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0004_0000 0x0002_0000 0x0001_0000 0x0000_0000 sa2-3 (8 kbx2) 0x0000_0000 sa2-3 (8 kbx2) 0x0000_0000 sa2-3 (8 kbx2) flash(work area) 32 kbytes flash(work area) 32 kbytes sa8 (48 kb) sa8 (48 kb) sa9 (64 kb) flash(main area) 256 kbytes flash(main area) 128 kbytes flash(main area) 64 kbytes sa8 (48 kb) sa9-11 (64 kbx3) reserved reserved reserved sram0 8kbytes reserved sa4-7 (8 kbx4) flash(work area) 32 kbytes sa4-7 (8 kbx4) sram0 8kbytes reserved reserved sa4-7 (8 kbx4) reserved sram1 8kbytes reserved sram1 8kbytes reserved sram0 16kbytes sram1 16kbytes reserved reserved reserved
document number: 002 - 05631 rev * b page 57 of 128 mb9a b 40 nb series peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash m emory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x40 01_5fff dual timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_4fff apb1 reserved 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff reserved 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x 4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check register 0x4003_2000 0x4003_2fff lcdc 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_ 4fff hdmi - cec/remote control receiver 0x4003_5000 0x4003_5 7 ff low - voltage detector 0x4003_5 800 0x4003_5 f ff deep standby mode controller 0x4003_6000 0x4003_6fff usb clock generator 0x4003_7000 0x4003_7fff reserved 0x4003_8000 0x4003_8fff multi - fu nction serial 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external memory interface 0x4004_0000 0x4004_ffff ahb usb ch . 0 0x4 005_0000 0x4005_ffff reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_ 1 000 0x4 1ff _ f fff reserved
document number: 002 - 05631 rev * b page 58 of 128 mb9a b 40 nb series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the l leve l. ? initx=1 this is the period when the initx pin is the h level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to 0. ? spl=1 this is the status that the standby pin level setting b it (spl) in the standby mode control register (stb_ctl) is set to 1. ? input enabled indicates that the input function can be used. ? internal input fixed at 0 this is the status that the input function cannot be used. internal input is fixed at l. ? hi - z indica tes that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the general - purpose i/o port.
document number: 002 - 05631 rev * b page 59 of 128 mb9a b 40 nb series list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / interna l input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input en abled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal inp ut fixed at 0 gpio selected external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 maintain previous state hi - z / internal input fixed at 0 ma intain previous state main crystal oscillator output pin hi - z / internal input fixed at 0/ or input enable d hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], , hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], , hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], , hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], , hi - z / internal input fixed at 0 maintain previous state/ when oscillation stop s [1], , hi - z / internal input fixed at 0 c initx input pin pull - up / input enabled pull - up / input enabled pul l - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled in put enabled input enabled input enabled input enabled
document number: 002 - 05631 rev * b page 60 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled gpio selected hi - z / input enabled gpio selected f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / inter nal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input e nabled input enabled input enabled input enabled g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal in put fixed at 0 gpio selected external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 maintain previous state hi - z/ internal input fixed at 0 mai ntain previous state sub crystal oscillator output pin hi - z / internal input fixed at 0/ or input enable hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state maintain previous state /whe n oscillation stop s [ 2 ] , hi - z / internal input fixed at 0 maintain previous state /whe n oscillation stop s [ 2 ] , hi - z / internal input fixed at 0 maintain previous state /whe n oscillation stop s [ 2 ] , hi - z / internal input fixed at 0 maintain previous state /whe n oscillation stop s [ 2 ] , hi - z / int ernal input fixed at 0 maintain previous state /whe n oscillation stop s [ 2 ] , hi - z / internal input fixed at 0
document number: 002 - 05631 rev * b page 61 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - h gpio selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected usb i/o pin setting disabled setting disabled setting disabled maintain previous state hi - z at trans - mission/ input enabled/ internal input fixed at 0 at reception hi - z a t trans - mission/ input enabled/ internal input fixed at 0 at reception hi - z / input enabled hi - z / input enabled hi - z / input enabled i nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maint ain previous state wkup input enabled hi - z / wkup input enabled gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected j jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected k resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected gpio selected
document number: 002 - 05631 rev * b page 62 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - l external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous s tate maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected m analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input en abled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled resource other than abo ve selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected gpio selected n analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled external interrupt enabled sele cted setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 resource othe r than above selected hi - z / internal input fixed at 0 gpio selected
document number: 002 - 05631 rev * b page 63 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - o trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 resource other than above selected hi - z hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected p anal og input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / in ternal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled trace selected setting disabled settin g disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 resource other than above selected hi - z / inte rnal input fixed at 0 gpio selected q analog input selected hi - z hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / i nternal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analo g input enabled trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 external interrupt enabled selected maintain previous state resource o ther than above selected hi - z / internal input fixed at 0 gpio selected
document number: 002 - 05631 rev * b page 64 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - r analog input selected hi - z hi - z / internal input fixed at 0 / analog input en abled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixe d at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected internal input fixed at 0 external interrupt enabled selected gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 resource o ther than above selected hi - z / internal input fixed at 0 gpio selected s cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous s tate maintain previous state resource o ther than above selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal inpu t fixed at 0 gpio selected gpio selected t cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio sele cted internal input fixed at 0 hi - z / internal input fixed at 0 resource o ther than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at 0 gpio selected
document number: 002 - 05631 rev * b page 65 of 128 mb9a b 40 nb series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or s leep mode state deep standby rtc mode or deep standby s top mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable powe r supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - u resource selected hi - z hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 gpio sel ected v external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio s elected internal input fixed at 0 resource o ther than above selected hi - z hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected w analog input selected hi - z hi - z / internal inp ut fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input ena bled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled hi - z / internal input fixed at 0 / analog input enabled resource o ther than above selected setting disabled setting disabled setting dis abled maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 gpio selected x resource selected hi - z hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 maintain previous state maintain previous state hi - z / internal input fixed at 0 gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected y external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at 0 hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 resource o ther than above selected hi - z hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 hi - z / internal input fixed at 0 gpio selected 1 : oscillation is stopped at s ub timer mode , low - sp eed cr timer mode, rtc mode, stop mode , deep standby rtc mode , and deep standby stop mode. 2: oscillation is stopped at stop mode and deep standby stop mode .
document number: 002 - 05631 rev * b page 66 of 128 mb9a b 40 nb series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage [1],[2] v cc v ss - 0.5 v ss + 4.6 v analog power supply voltage [1],[3] av cc v ss - 0.5 v ss + 4.6 v analog reference voltage [1],[3] avrh v ss - 0.5 v ss + 4.6 v lcd input voltage [1],[3] vv0 to vv4 v ss - 0.5 v ss + 4.6 v input v oltage [1] v i v ss - 0.5 v cc + 0.5 ( 4.6 v) v v ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage [1] v ia v ss - 0.5 av cc + 0.5 ( 4.6 v) v output voltage [1] v o v ss - 0.5 v cc + 0.5 ( 4.6 v) v l level maximum output current [4] i ol - 10 ma 39 ma p81/udp0 , p80/udm0 pin s l level average output current [5] i olav - 4 ma 10.5 ma [ 7 ] 27 ma [ 8 ] l level total maximum output current i ol - 100 ma l level total average output current [6] i olav - 50 ma h level maximum output current [4] i oh - - 10 ma 39 ma p81/udp0 , p80/udm0 pin s h level average output current [5] i ohav - - 4 ma 12 ma [ 7 ] 27 ma [ 8 ] h level total maximum output current i oh - - 100 ma h level total average output current [6] i ohav - - 50 ma power consu mption p d - 300 mw storage temperature t stg - 55 + 150 c 1 : these parameters are based on the condition that v ss = av ss = 0v. 2 : v cc must not drop below v ss - 0.5v. 3 : ensure that the voltage does not to exceed v cc + 0. 5 v, for example, when the power is turned on. 4 : the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. 5 : the average output current is defined as the average current value flowing through any one of the corresponding p ins for a 100 ms period. 6 : the total average output current is defined as the average current value flowing through all of corresponding pins for a 100m s. 7 : when p81/udp0 and p80/udm0 pins are used as gpio (p81, p80). 8 : t hen p81/udp0 and p80/udm0 pins a re used as usb (udp0, udm0). warning: ? semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.do not exceed any of these ratings.
document number: 002 - 05631 rev * b page 67 of 128 mb9a b 40 nb series 12.2 reco mmended operating conditions (v ss = av ss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 1.65 [6] 3.6 v [1], [4] 3.0 [6] 3.6 [2] 2.2 [6] 3.6 [1], [3] lcd input voltage v vv4 - 2.2 v cc v analog power supply voltage av cc - 1.65 3.6 v av cc = v cc analog reference voltage avrh - 2.7 av cc v av cc 2.7 v av cc av cc v av cc < 2.7 v avrl - av ss av ss v smoothing capacitor c s - 1 10 f f or regulator [5] operating t emperature t a - - 40 + 85 c 1 : when p81/udp0 and p80/udm0 pins are used as gpio (p81, p80). 2 : when p81/udp0 and p80/udm0 pins are u sed as usb (udp0, udm0). 3 : when lcd controller is used. 4 : when lcd controller is not used. 5 : see c pin in handling devices for the connection of the smoothing capacitor. 6 : in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. warning: ? the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 05631 rev * b page 68 of 128 mb9a b 40 nb series 12.3 dc characteristics 12.3.1 current rating (v cc = av cc = 1.65 v to 3.6 v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks typ [3] max [4] power supply current i cc vcc pll rrun mode cpu: 40 mhz, peripheral: 40 mhz 15.5 21 ma [1], [5] cpu: 40 mhz, peripheral: the clock stops nop operation 8.7 12 ma [1], [5] high - speed cr rrun mode cpu/ peripheral: 4 mhz [ 2 ] 1.8 2.9 ma [1] sub rrun mode cpu/ peripheral: 32 khz 110 680 a [1], [6] low - speed cr run mode cpu/ peripheral: 100 kh z 125 700 a [1] i ccs pll sleep mode peripheral: 40 mhz 9 12.5 ma [1], [5] high - speed cr sleep mode peripheral: 4 mhz [ 2 ] 0.8 1.6 ma [1] sub sleep mode peripheral: 32 khz 96 670 a [1], [6] low - speed cr sleep mode peripheral: 100 khz 110 680 a [1] 1 : when a l l ports are fixed. 2 : when setting it to 4 mhz by trimming. 3 : t a =+25c, v cc = 3.6 v 4 : t a =+ 85 c, v cc = 3.6 v 5 : when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) 6: when using the cryst al oscillator of 32 khz (including the current consumption of the oscillation circuit )
document number: 002 - 05631 rev * b page 69 of 128 mb9a b 40 nb series parameter symbol pin name conditions value unit remarks typ [2] max [2] power supply current i cct vcc main timer mode t a = + 25 c , when lvd is off 2.1 2.5 ma [ 1], [3] t a = + 85 c , when lvd is off - 3.4 ma [1], [3] sub timer mode t a = + 25 c , when lvd is off 12 35 a [1], [4] t a = + 85 c , when lvd is off - 330 a [1], [4] i ccr rtc mode t a = + 25 c , when lvd is off 9.8 29 a [1], [4] t a = + 85 c , when lvd is off - 280 a [1], [4] i cch stop mode t a = + 25 c , when lvd is off 9 28 a [1] t a = + 85 c , when lvd is off - 270 a [1] i cchd deep standby stop mode t a = + 25 c , when lvd is off, when ram is off 1.25 7 a [1], [4], [5] t a = + 25 c , when lvd is off, when ram is on 5.3 18 a [1], [4], [5] t a = + 85 c , when lvd is off, when r am is off - 70 a [1], [4], [5] t a = + 85 c , when lvd is off, when ram is on 100 a [1], [4], [5] i cc rd deep standby rtc mode t a = + 25 c , when lvd is off, when ram is off 1.9 9 a [1], [5] t a = + 25 c , when lvd is off, when ram is on 5.9 20 a [1], [5] t a = + 85 c , when lvd is off, when ram is off - 75 a [1], [5] t a = + 85 c , when lvd is off, when ram is on 105 a [1], [5] 1 : when a l l ports are fixed. 2 : v cc = 3.6 v 3 : when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit ) 4 : when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit ) 5 : ram on/off setting is on - chip sram only.
document number: 002 - 05631 rev * b page 70 of 128 mb9a b 40 nb series low - v oltage d etection current (v cc = 1.65 v to 3.6 v, v ddi = 1.1v to 1.3v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation for reset v cc = 3.6 v 0.13 0.3 a at not detect at operation for interrupt v cc = 3.6 v 0.13 0.3 a at not detect flash memory current (v cc = 1.65 v to 3.6 v, v ddi = 1.1v to 1.3v, v ss = 0v, t a = - 40c to + 85 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 9.5 11.2 ma * *: the current at which to write or erase flash memory, i ccflash is added to i cc . a/d converter current (v cc = v cc28 = av cc = 1.65v to 3.6v, v ddi = 1.1v to 1.3v, v ss = av ss = 0v, t a = - 40c to +85c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.27 0.42 ma at stop 0.03 10 a reference power supply current i ccavrh avrh at 1unit operation avrh=3.6 v 0.72 1.29 ma at stop 0.02 2.6 a
document number: 002 - 05631 rev * b page 71 of 128 mb9a b 40 nb series 12.3.2 pin characteristics (v cc = av cc = 1.65v to 3.6v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value uni t remark s min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0, md1 v cc 2.7 v v cc 0.8 - v cc + 0.3 v v cc < 2.7 v v cc 0.7 5v tolerant input pin v cc 2.7 v v cc 0.8 - v ss + 5.5 v v cc < 2.7 v v cc 0.7 l level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0, md1 v cc 2.7 v v ss - 0.3 - v cc 0.2 v v cc < 2.7 v v cc 0.3 5v tolerant input pin v cc 2.7 v v ss - 0.3 - v cc 0.2 v v cc < 2.7 v v cc 0.3 h level output voltage v oh 4ma type v cc 2.7 v , i oh = - 4 ma v cc - 0.5 - v cc v v cc < 2.7 v , i oh = - 2 ma v cc - 0.45 the pin doubled as usb i/o v cc 2.7 v , i oh = - 12 ma v cc - 0.4 - v cc v v cc < 2.7 v , i oh = - 6.5 ma l level output voltage v ol 4ma type v cc 2.7 v , i ol = 4 ma v ss - 0.4 v v cc < 2.7 v , i ol = 2 ma the pin doubled as usb i/o v cc 2.7 v , i ol = 10.5 ma v ss - 0.4 v v cc < 2.7 v , i ol = 5 ma input leak current i il - - - 5 - + 5 a cec0, cec1 v cc = av cc = av rh = v ss = av ss = 0 .0 v - - +1.8 a pull - up resistor value r pu pull - up pin v cc 2.7 v 21 33 66 k v cc < 2.7 v - - 134 input capacitance c in other than vcc, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 05631 rev * b page 72 of 128 mb9a b 40 nb series 12.4 lcd characteristics (v cc = 2.2v to 3.6v , v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min typ max vv0 to vv3 o utput voltage (1/4 bias) v vv0 vv0 when using internal dividing resistor 0 - v vv4 5% v v vv1 vv1 v vv4 1/4 - 10% - v vv4 1/4+10% v vv2 vv2 v vv4 1/2 - 10% - v vv4 1/2+10% v vv3 vv3 v vv4 3/4 - 10% - v vv4 3/4+10% vv0 to vv3 o utput voltage (1/3 bias) v vv0 vv0 when using internal dividing resistor 0 - v vv4 5% v v vv1 vv1 v vv4 1/3 - 10% - v vv4 1/3+10% v vv2 vv2 v v v4 2/3 - 10% - v vv4 2/3+10% v vv3 vv3 v vv4 2/3 - 10% - v vv4 2/3+10% vv0 to vv3 o utput voltage (1/2 bias) v vv0 vv0 when using internal dividing resistor 0 - v vv4 5% v v vv1 vv1 v vv4 1/2 - 10% - v vv4 1/2+10% v vv2 vv2 v vv4 1/2 - 10% - v vv4 1/2+10% v vv3 vv3 v vv4 1/2 - 10% - v vv4 1/2+10% vv4 active current (1/4 bias) i r100k vv4 when using 100 k internal dividing resistor - 10 20 a i r10k vv4 when using 10 k internal dividing resistor - 100 160 a vv4 active current (1/3 bias) i r100k vv4 when using 100 k internal dividing resistor - 12 30 a i r10k vv4 when using 10 k internal divi ding resistor - 120 180 a vv4 active current (1/2 bias) i r100k vv4 when using 100 k internal dividing resistor - 18 40 a i r10k vv4 when using 10 k internal dividing resistor - 180 270 a vv4 static current i off_vv4 vv4 when lcd stops - 0.5 1. 5 a vv0 output voltage in using external resistor v vv0e vv0 i ol =1 ma - - 0.66 v
document number: 002 - 05631 rev * b page 73 of 128 mb9a b 40 nb series 12.5 ac characteristics 12.5.1 main clock input characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbo l pin name conditions value unit remarks min max input frequency f ch x0, x1 v cc 2.7 v 4 48 mhz when crystal oscillator is connected v cc < 2.7 v 4 20 - 4 48 mhz when using external clock input clock cycle t cylh - 20.83 250 ns when using external clock input clock pulse width - p wh/tcylh, pwl/tcylh 45 55 % when using external clock input clock rising time and falling time t cf, t cr - - 5 ns when using external clock internal operating clock [1] frequency f cm - - - 40 mhz master clock f cc - - - 40 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock [2] f cp1 - - - 40 mhz apb1 bus clock [2] f cp 2 - - - 40 mhz apb2 bus clock [2] internal operating clock [1] cycle time t cycc - - 25 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock [2] t cycp1 - - 25 - ns apb1 bus clock [2] t cycp2 - - 25 - ns apb2 bus clock [2] 1 : for more information about each internal operating clock , see chapter 2 - 1 : clock in fm3 family peripheral manual . 2 : for about each apb bus which each peripheral is connected to , see block diagram in this datasheet. x0
document number: 002 - 05631 rev * b page 74 of 128 mb9a b 40 nb series 12.5.2 sub clock in put characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a, x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz whe n using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - pwh/tcyll, pwl/tcyll 45 - 5 5 % when using external clock 12.5.3 built - in cr oscillation characteristics built - in high - speed cr (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 2 5 c v cc 2.7 v 3.96 4 4.04 mhz when trimming [1] t a = + 25 c v cc < 2.7 v 3.9 4 4.1 t a = - 40 c to + 85 c 3.84 4 4.16 t a = - 40 c to + 85 c 2.8 - 5.2 when not trimming frequency stabilization time t crwt - - - 30 s [2] 1 : in the case of using the va lues in cr trimming area of flash memory at shipment for frequency/temperature trimming. 2: this is the time to stabilize the frequency of high - speed cr clock after setting trimming value. this period is able to use high - speed cr clock as source clock. x0 a
document number: 002 - 05631 rev * b page 75 of 128 mb9a b 40 nb series b uilt - in low - speed cr (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz 12.5.4 operating conditions of main and usb pll operating conditions of main and usb pll (in the case of using main clock for input of pll) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time [1] (lock up time) t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiple rate - 5 - 37 multiple pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency [2] f clkpll - - 40 mhz usb clock frequency [3] f clkspll - - 48 mhz after the m frequency division 1: time from when the pll starts operating until the oscillation stabilizes. 2: for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family peripheral manual. 3: for more information about usb clock, see chapter 2 - 2 : usb clock generation in fm3 family peripheral manual communication macro part. operating conditions of main pll (in the case of using the built - in high - speed cr for the input clock of the main pll ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter sy mbol value unit remarks min typ max pll oscillation stabilization wait time [1] (lock up time) t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiple rate - 19 - 35 multiple pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency [2] f clkpll - - 40 mhz 1: time from when the pll starts operating until the osc illation stabilizes. 2: for more information about main pll clock (clkpll), see chapter 2 - 1 : clock in fm3 family peripheral manual. note: ? make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency /temperature has be en trimmed. when setting pll multiple rate, please take the accuracy of the built - in h igh - speed cr clock into account and prevent the master clock from exceeding the maximum frequency.
document number: 002 - 05631 rev * b page 76 of 128 mb9a b 40 nb series 12.5.5 reset inpu t characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns main clock (clkmo) k divider pll input cl ock usb pll m divider usb clock n divider usb pll connection pll macro oscillation clock high - speed cr clock (clkhc) pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection main clock (clkmo) k divider
document number: 002 - 05631 rev * b page 77 of 128 mb9a b 40 nb series 12.5.6 power - on reset timing (v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 1 - - ms *1 power ramp rate dv/dt vcc:0.2 v to 1.65 v 0.2 - 1000 m v/ s *2 time until releasing power - on reset t prt - 1.34 - 16.09 ms *1: v cc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of co ld start (t off >1 ms). note: ? if t off cannot be satisfied designs must assert external reset(initx) at power - up and at any brownout event per 1 3 . 5. 5 . reset inpu t characteristics . glossary ? vd h : det ection voltage of low voltage detection reset. see 12.8 low - voltage detection characteristics v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 1 . 6 5 v
document number: 002 - 05631 rev * b page 78 of 128 mb9a b 40 nb series 12.5.7 external bus timing external bus clock out put c haracteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions valu e unit min max out put frequency t cycle mclkout* v cc 2.7 v - 40 mhz v cc < 2.7 v - 20 mhz *: the external bus clock output (mclkout) is a divided clock of hclk. for more information about setting of clock divider , see chapter 12 : external bus interface in fm3 family peripheral manual. when external bus clock is not output, this characteristic does not give any effect on external bus operation. external bus signal input/output characteristics (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c t o + 85 c) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v input signal output signal mclkout v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 05631 rev * b page 79 of 128 mb9a b 40 nb series separate bus access asynchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex v cc 2.7 v mclkn - 3 - ns v cc < 2.7 v mcsx address output delay time t csl C av mcsx[7:0], mad[24:0] v cc 2.7 v - 9 +9 ns v cc < 2.7 v - 12 +12 moex address hold time t oeh - ax moex, mad[24:0] v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclk m+12 mcsx moex delay time t cs l - oe l moex, mcsx[7:0] v cc 2.7 v mclkm - 9 mclkm+9 ns v cc < 2.7 v mclkm - 12 mclkm+12 moex mcsx time t oeh - c sh v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclkm+12 mcsx mdqm delay time t cs l - r dqml mcsx, mdqm[1:0] v cc 2.7 v mclkm - 9 mclkm+9 ns v cc < 2.7 v mclkm - 12 mclkm+12 data set up moex time t ds - oe moex, madata[15:0] v cc 2.7 v 30 - ns v cc < 2.7 v 38 - moex data hold time t dh - oe moex, madata[15:0] v cc 2.7 v 0 - ns v cc < 2.7 v m wex min pulse width t wew mwex v cc 2.7 v mclkn - 3 - ns v cc < 2.7 v mwex address output delay time t weh - ax mwex, mad[24:0] v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclkm+12 mcsx mwex delay time t csl - wel mw ex, mcsx[7:0] v cc 2.7 v mclkn - 9 mclkn+9 ns v cc < 2.7 v mclkn - 12 mclkn+12 mwex mcsx delay time t weh - csh v cc 2.7 v 0 mclkm+9 ns v cc < 2.7 v mclkm+12 mcsx mdqm delay time t cs l - w dqml mcsx, mdqm[1:0] v cc 2.7 v mclkn - 9 mcl kn+9 ns v cc < 2.7 v mclkn - 12 mclkn+12 mwex data output time t csl - dv mcsx, madata[15:0] v cc 2.7 v mclk - 9 mclk+9 ns v cc < 2.7 v mclk - 12 mclk+12 mwex data hold time t weh - dx mwex, madata[15:0] v cc 2.7 v 0 mclkm+9 ns v cc < 2. 7 v mclkm+12 note: ? w hen the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16).
document number: 002 - 05631 rev * b page 80 of 128 mb9a b 40 nb series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex
document number: 002 - 05631 rev * b page 81 of 128 mb9a b 40 nb series separate bus access synchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max address delay time t av mclk, mad[24:0] v cc 2.7 v 1 12 ns v cc < 2.7 v 13 mcsx delay time t csl mclk, mcsx[7:0] v cc 2.7 v 1 12 ns v cc < 2.7 v t cs h v cc 2.7 v 1 12 ns v cc < 2.7 v moex delay time t rel mclk, moex v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t reh v cc 2.7 v 1 9 ns v cc < 2.7 v 12 data set up mclk time t ds mclk, madata[15:0] v cc 2.7 v 24 - ns v cc < 2.7 v 37 mclk data hold time t dh mclk, madata[15:0] v cc 2.7 v 0 - ns v cc < 2.7 v mwex delay time t wel mclk, mwex v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t we h v cc 2.7 v 1 9 ns v cc < 2.7 v 12 mdqm[1:0] delay time t dqml mclk, mdqm[1:0] v cc 2.7 v 1 9 ns v cc < 2.7 v 12 t dqmh v cc 2.7 v 1 9 ns v cc < 2.7 v 12 mclk data output time t ods mclk, madata[15:0] v cc 2.7 v mclk + 1 mclk + 18 ns v cc <2.7 v mclk + 24 mclk data hold time t od mclk, madata[15:0] v cc 2.7 v 1 18 ns v cc < 2.7 v 24 note: ? w hen the external load capacitance c l = 30 pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex
document number: 002 - 05631 rev * b page 82 of 128 mb9a b 40 nb series multiplexed bus access asynchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male, madata[15:0] v cc 2.7 v - 2 +10 ns v cc < 2.7 v +20 multiplexed a ddress hold time t c hmadh v cc 2.7 v mclk n+0 mclk n+10 ns v cc < 2.7 v mclk n+0 mclk n+20 note: ? w hen the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16) . mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 05631 rev * b page 83 of 128 mb9a b 40 nb series multiplexed bus access synchronous sram mode (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit re marks min max male delay time t chal mclk , ale v cc 2.7 v 1 9 ns v cc < 2.7 v 1 2 ns t chah v cc 2.7 v 1 9 ns v cc < 2.7 v 12 ns mclk multiplexed address delay time t chmadv m clk, madata[15:0] v cc 2.7 v 1 t od ns v cc < 2.7 v mclk multiplexed data output time t chmad x v cc 2.7 v 1 t od ns v cc < 2.7 v note: ? w hen the external load capacitance c l = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 05631 rev * b page 84 of 128 mb9a b 40 nb series external ready input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk, mrdy v cc 2.7 v 23 - ns v cc < 2.7 v 37 when rdy is input when rdy is rel ease d mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi 2 cycles t rdyi 0.5vcc
document number: 002 - 05631 rev * b page 85 of 128 mb9a b 40 nb series 12.5.8 base timer input timing timer input timing (v cc = 1.65 v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck, tin) - 2 t cycp - ns trigger input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit rem arks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to , see block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 05631 rev * b page 86 of 128 mb9a b 40 nb series 12.5.9 csio /uart timing csio (spi = 0, scinv = 0) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sck x master mode 4t cycp - 4t cycp - n s sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 36 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - n s serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , sotx - 50 - 33 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf.
document number: 002 - 05631 rev * b page 87 of 128 mb9a b 40 nb series master mode slave mode t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin
document number: 002 - 05631 rev * b page 88 of 128 mb9a b 40 nb series csio (spi = 0, scinv = 1 ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max mi n max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 36 - ns sck sin hold time t sl ixi sckx , sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , sotx - 50 - 33 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number.for example, t he combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance cl = 30 pf.
document number: 002 - 05631 rev * b page 89 of 128 mb9a b 40 nb series master mode slave mode t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t sl ixi sck sot sin
document number: 002 - 05631 rev * b page 90 of 128 mb9a b 40 nb series csio (spi = 1, scinv = 0 ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 3 0 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 36 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns sot sck delay time t sovli sckx , sotx 2t cycp - 34 - 2t cycp - 34 - ns serial clock l pulse width t slsh sckx slave mode 2t cy cp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , s ot x - 50 - 33 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is co nnected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30 pf.
document number: 002 - 05631 rev * b page 91 of 128 mb9a b 40 nb series master mode slave mode *: changes when writing to tdr register t f t r t sl sh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi sck sot sin
document number: 002 - 05631 rev * b page 92 of 128 mb9a b 40 nb series csio (spi = 1, scinv = 1 ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions v cc < 2.7 v v cc 2.7 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 36 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns sot sck delay time t sovhi sckx , sotx 2t cycp - 34 - 2t cycp - 34 - ns serial clock l pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , s ot x - 50 - 33 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time t f sckx - 5 - 5 ns sck rising time t r sckx - 5 - 5 ns notes: ? the above characteristics apply to clock synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is connected to , see block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance cl = 30 pf.
document number: 002 - 05631 rev * b page 93 of 128 mb9a b 40 nb series master mode slave mode uart external clock input (ext = 1 ) (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min max serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck falling time t f - 5 ns sck rising time t r - 5 ns t shsl v i l v i l v i l v ih v ih v ih t r t f t slsh t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin s ck
document number: 002 - 05631 rev * b page 94 of 128 mb9a b 40 nb series 12.5.10 external input timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name condit ions value unit remarks min max input pulse width t inh, t inl adtg - 2 t cycp [1] - ns a/d converter trigger input intxx, nmix [2] 2 t cycp + 100 [1] - ns external interrupt nmi [3] 500 - ns wkupx [4] 600 - ns deep standby wake up 1 : t cycp i ndicates the apb bus clock cycle time. about the apb bus number which the multi - function timer is connected to , see block diagram in this data sheet. 2 : when in run mode, in sleep mode. 3 : when in timer mode, in rtc mode, in stop mode. 4 : when in deep standby rtc mode, in deep standby stop mode.
document number: 002 - 05631 rev * b page 95 of 128 mb9a b 40 nb series 12.5.11 i 2 c timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) [1] 0 100 0 400 khz (repeated) sta rt condition hold time sda scl t hdsta 4.0 - 0.6 - s scl clock l width t low 4.7 - 1.3 - s scl clock h width t high 4.0 - 0.6 - s (repeated) start condition setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hd dat 0 3.45 [2] 0 0.9 [3] s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between stop condition and start condition t buf 4.7 - 1.3 - s noise filter t sp - 2 t cyc p [4] - 2 t cycp [4] - ns 1: r and c represent the pull - up resistor and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistor and i ol indicates v ol guaranteed current. 2: the maximum t hddat m ust satisfy that it does n o t extend at least l period (t low ) of device's scl signal. 3: a fast - mode i 2 c bus device can be used on a s tandard - mode i 2 c bus system as long as the device satisfies the requirement of t sudat 250 ns. 4: t cycp is the apb bus clock cycle time.about the apb bus number that i 2 c is connected to, see block diagram in this data sheet. to use s tandard - mode, set the apb bus clock at 2 mhz or more.to use fast - m ode, set the apb bus clock at 8 mhz or more. sda s cl
document number: 002 - 05631 rev * b page 96 of 128 mb9a b 40 nb series 12.5.12 etm timing (v cc = 1.65v t o 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk, traced[3:0] v cc 2.7 v 2 11 ns v cc < 2.7 v 2 15 traceclk frequency 1/ t trace traceclk v cc 2.7 v - 40 mhz v cc < 2.7 v - 20 mhz traceclk clock cycle t trace v cc 2.7 v 25 - ns v cc < 2.7 v 50 - ns note: ? when the external load capacitance c l = 30 p f. hclk traceclk traced[3:0]
document number: 002 - 05631 rev * b page 97 of 128 mb9a b 40 nb series 12.5.13 jtag timing (v cc = 1.65v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck, tms, tdi v cc 2.7 v 15 - ns v cc < 2.7 v tms, tdi hold time t jtagh tck, tms, tdi v cc 2.7 v 15 - ns v cc < 2.7 v tdo delay time t jtagd tck, tdo v cc 2.7 v - 25 ns v cc < 2.7 v - 45 note: ? when the external load capacitance c l = 30 pf. tck tms/tdi tdo
document number: 002 - 05631 rev * b page 98 of 128 mb9a b 40 nb series 12.6 12 - bit a/d converter electrical c haracteristics for the a/d c onverter (v cc = av cc = 1.65v to 3.6v, v ss = av ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 2 4.5 lsb differential nonlinearity - - - 2.2 2.5 lsb zero transition voltage v zt an xx - 6 15 mv full - scale transi tion voltage v fst an xx - avrh 6 avrh 15 mv conversion time - - 2.0 [1] - - s av cc 2.7 v 4.0 [1] - - 1.8 v < av cc < 2.7 v 10 [1] - - 1.65 v < av cc < 1.8 v sampling time [2] t s - 0.6 - 10 us av cc 2.7 v 1.2 - 1.8 v < av cc < 2.7 v 3.0 - 1.65v < av cc < 1.8v compare clock cycle [3] t cck - 100 - 1000 ns av cc 2.7 v 200 1.8 v < av cc < 2.7 v 500 1.65 v < av cc < 1.8 v state transition time to operation permission t stt - - - 1.0 s power supply current (analog + digital) - av cc - 0.27 0.42 ma a/d 1unit operation - 0.03 10 a when a/d stops reference power supply current (between avrh to avss) - avrh - 0.72 1.29 ma a/d 1unit operation avrh=3.6 v - 0.02 2.6 a when a/d stops analog input capacity c ain - - - 9.4 pf an alog input resistor r ain - - - 2.2 k av cc 2.7v 5.5 1.8 v < av cc < 2.7 v 10.5 1.65 v < av cc < 1.8 v interchannel disparity - - - - 4 lsb analog port input leak current - an xx - - 5 a analog input voltage - an xx av ss - avrh v reference voltage - avrh 2.7 - av cc v av cc 2.7 v av cc av cc < 2.7 v - avrl av ss - av ss v 1 : the conversion time is the value of sampling time (t s ) + compare time (t c ). the condition of the minimum conversion time is the following. av cc 2.7 v, h clk= 40 mhz sampling time: 0.6 s , compare time: 1.4 s 1.8 v < av cc < 2.7 v , hclk= 40 mhz sampling time: 1.2 s, compare time: 2.8 s 1.65 v < av cc < 1.8 v , hclk= 40 mhz sampling time: 3 s, compare time: 7 s ensure that it satisfies the valu e of the sampling time (t s ) and compare clock cycle (t cck ). for setting of the sampling time and the compare clock cycle, see chapter 1 - 1 : a/d converter in fm3 family peripheral manual analog macro port . the register setting of the a/d converter are refl ected in the operation according to the apb bus clock timing. the sampling clock and compare clock is generated from the base clock (hclk). about the apb bus number which the a/d converter is connected to, see block diagram in this data sheet. 2 : a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy ( equation 1 ). 3 : the compare time ( t c ) is the value of ( equation 2).
document number: 002 - 05631 rev * b page 99 of 128 mb9a b 40 nb series (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time[ns] r ain : input resistor of a/d[k ] = 2.2 k at 2.7 v < av cc < 3.6 v input resistor of a/d[k ] = 5.5 k at 1.8 v < av cc < 2.7 v input resistor of a/d[k ] = 10.5 k at 1.65 v < av cc < 1.8 v c ain : input capacity of a/d[pf] = 9.4 pf at 1.65 v < av cc < 3.6 v r ext : output impedance of external circuit[k ] (equation 2 ) t c = t cck 14 t c : compare time t cck : compare clock cycle analog signal source an xx analog input pin c omp arator r ext r ain c ain
document number: 002 - 05631 rev * b page 100 of 128 mb9a b 40 nb series definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonlinearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conve rsion characteristics. ? differential nonlinearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. linearity error of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential linearity error of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n: a/d converter digital output value. v zt : voltage at which the digital output changes from 0x000 to 0x001. v fst : vol tage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonlinearity differential nonlinearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 05631 rev * b page 101 of 128 mb9a b 40 nb series 12.7 usb c haracteristics (v cc = 3.0v to 3.6v, v ss = 0v, t a = - 40 c to + 85 c) parameter symbol pin name conditions value u nit remarks m in m ax input characteristics input h level voltage v ih udp0, udm0 - 2.0 v cc + 0.3 v [1] input l level voltage v il - v ss - 0.3 0.8 v [1] differential input sensitivity v di - 0.2 - v [2] different common mode range v cm - 0.8 2 .5 v [2] output characteristics output h level voltage v oh external pull - down resistor = 15k 2.8 3.6 v [3] output l level voltage v ol external pull - up resistor = 1.5k 0 0.3 v [3] crossover voltage v crs - 1.3 2.0 v [4] rising time t fr full - speed 4 20 ns [5] falling time t ff full - speed 4 20 ns [5] rising/falling time matching t frfm full - speed 90 111.11 % [5] output impedance z drv full - speed 28 44 [5] rising time t lr low - speed 75 300 ns [7] falling time t lf low - speed 75 300 ns [7] rising/ f alling time matching t lrfm low - speed 80 125 % [7] 1 : the switching threshold volt age of single - end - receiver of usb i/o buffer is set as within v il (max) = 0.8v, v ih (min) = 2.0 v (ttl input standard). there are some hysteresis to lower noise sensitivity. 2 : u se the differential - receiver to receive the usb differential data signal. the differential - receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 v to 2.5 v to the local ground reference level. above voltage range is the common mode input voltage range. common mode input voltage [v] 3 : the output drive capability of the driver is below 0.3 v at low - state (v ol ) (to 3.6 v and 1.5 k load), and 2.8 v or above (to ground and 15 k load) at high - state (v oh ). 4 : the cross voltage of the external differential output signal (d + /d ? ) of usb i/o buffer is within 1.3 v to 2.0 v. minimum differential input sensitivity [v]
document number: 002 - 05631 rev * b page 102 of 128 mb9a b 40 nb series 5 : they indicate the rising time (trise) and falling time (tfall) of the full - speed d ifferential data signal. they are defined by the time between 10% and 90 % of the output signal voltage. for full - speed buffer, tr/tf ratio is regulated as within 10 % to minimize rfi emission. 6 : usb full - speed connection is performed via twist pair cable shield with 90 15% characteristic im pedance (differential mode). usb standard defines that output impedance of usb driver must be in range from 28 to 44 . so, discrete series resistor (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i /o, use it with 25 to 30 (recommendation value 27 ) series resistor rs. v crs specified range rising time falling time
document number: 002 - 05631 rev * b page 103 of 128 mb9a b 40 nb series rs series resistor 25 to 30 series resistor of 27 (recommendation value) must be added. and, use resistance with an uncertainty of 5% by e24 sequence. 7 : they indicate the rising time (trise) and falling time (tf all) of the low - speed differential data signal. they are defined by the time between 10 % and 90 % of the output signal voltage. see figure ? low - speed load (compliance load) for conditions of the external load. mount it as external resistor. 28 to 44 equiv. imped. 28 to 44 equiv. imped. rising time falling time
document number: 002 - 05631 rev * b page 104 of 128 mb9a b 40 nb series low - speed load (upstream port load) - reference 1 low - speed load (downstream port load) - reference 2 low - speed load (compliance load) c l = 50pf to 150pf c l = 50pf to 150pf c l = 200pf to 600pf c l = 200pf to 600pf c l = 200pf to 450pf c l = 200pf to 450pf
document number: 002 - 05631 rev * b page 105 of 128 mb9a b 40 nb series 12.8 low - v oltage d etection c haracteristics low - v oltage d etection r eset (t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr [1] = 00000 1.38 1.50 1.6 0 v when voltage dro ps released voltage vdh 1.43 1.55 1.65 v when voltage rises detected voltage vdl svhr [1] = 00001 1.43 1.55 1.65 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 00010 1.47 1.60 1 .73 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 00011 1.52 1.65 1.78 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected volta ge vdl svhr [1] = 00100 1.56 1.70 1.84 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 00101 1.61 1.75 1.89 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 00110 1.66 1.80 1.94 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 00111 1.70 1.85 2.00 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01000 1.75 1.90 2.05 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01001 1.79 1.95 2.11 v whe n voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01010 1.84 2.00 2.16 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl sv hr [1] = 01011 1.89 2.05 2.21 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01100 2.30 2.50 2.70 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when volt age rises detected voltage vdl svhr [1] = 01101 2.39 2.60 2.81 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01110 2.48 2.70 2.92 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 01111 2.58 2.80 3.02 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 10000 2.67 2.90 3.13 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 10001 2.76 3.00 3.24 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 1 0010 2.85 3.10 3.35 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises detected voltage vdl svhr [1] = 10011 2.94 3.20 3.46 v when voltage drops released voltage vdh s ame as svhr = 00000 value v when voltage rises lvd stabilization wait time t lvdw - - - 5200 t cycp [2] s lvd detection delay time t lvddl - - - 200 s 1 : the svhr bit of low - v oltage detection voltage control register (lvd_ctl) is initialized to 00000 by l ow - v oltage d etection r ese t . 2 : t cycp indic ates the apb2 bus clock cycle time.
document number: 002 - 05631 rev * b page 106 of 128 mb9a b 40 nb series 12.8.1 interrupt of l ow - v oltage d etection (t a = - 40 c to + 85 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 00100 1.56 1.70 1.84 v when voltage drops released voltage vdh 1.61 1.75 1.89 v when voltage rises detected voltage vdl svhi = 00101 1.61 1.75 1.89 v when voltage drops released voltage vdh 1.66 1.80 1.94 v when voltage rises detected voltage vdl svhi = 00110 1.66 1.80 1.94 v when voltage drops released voltage v dh 1.70 1.85 2.00 v when voltage rises detected voltage vdl svhi = 00111 1.70 1.85 2.00 v when voltage drops released voltage vdh 1.75 1.90 2.05 v when voltage rises detected voltage vdl svhi = 01000 1.75 1.90 2.05 v when voltage drops released volta ge vdh 1.79 1.95 2.11 v when voltage rises detected voltage vdl svhi = 01001 1.79 1.95 2.11 v when voltage drops released voltage vdh 1.84 2.00 2.16 v when voltage rises detected voltage vdl svhi = 01010 1.84 2.00 2.16 v when voltage drops released v oltage vdh 1.89 2.05 2.21 v when voltage rises detected voltage vdl svhi = 01011 1.89 2.05 2.21 v when voltage drops released voltage vdh 1.93 2.10 2.27 v when voltage rises detected voltage vdl svhi = 01100 2.30 2.50 2.70 v when voltage drops releas ed voltage vdh 2.39 2.60 2.81 v when voltage rises detected voltage vdl svhi = 01101 2.39 2.60 2.81 v when voltage drops released voltage vdh 2.48 2.70 2.92 v when voltage rises detected voltage vdl svhi = 01110 2.48 2.70 2.92 v when voltage drops re leased voltage vdh 2.58 2.80 3.02 v when voltage rises detected voltage vdl svhi = 01111 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 10000 2.67 2.90 3.13 v when voltage drops released voltage vdh 2.76 3.00 3.24 v when voltage rises detected voltage vdl svhi = 10001 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 10010 2.85 3.10 3.35 v when voltage d rops released voltage vdh 2.94 3.20 3.46 v when voltage rises detected voltage vdl svhi = 10011 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises lvd stabilization wait time t lvdw - - - 5200 t cycp * s lv d detection delay time t lvddl - - - 200 s *: t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 05631 rev * b page 107 of 128 mb9a b 40 nb series 12.9 flash memory write/erase characteristics 12.9.1 write / erase time ( v cc = 1.65v to 3.6v , t a = - 40 c to + 85 c ) parameter value unit remarks typ* max* sector eras e time large sector 1.1 2.7 s includ es write time prior to internal erase small sector 0.3 0.9 half word (16 - bit) write time 30 528 s not including system - level overhead time chip erase time 6.8 18 s includes write time prior to internal erase *: t he typical value is immediately after shipment , the maximam value is guarantee value under 10,000 cycle of erase/write . 12.9.2 write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1,000 20* 10,000 10* *: at average + 85 ? c
document number: 002 - 05631 rev * b page 108 of 128 mb9a b 40 nb series 12.10 return time from low - power consumption mode 12.10.1 return f actor: interrupt/wkup the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return c ount t ime ( v cc = 1.65 v to 3.6 v, v ddi = 1.1v to 1.3v, v ss = 0v, t a = - 40c to + 85 c ) parameter symbol value unit remarks typ max* sleep mode t icnt t cycc s high - speed cr timer mode, main timer mode, pll timer mode 40 80 s low - speed cr timer mode 350 700 s sub timer mode 690 880 s rtc mode, stop mode 278 523 s deep standby rtc mode deep standby stop mode 318 603 s when ram is off 278 523 s when ram is on *: the maximum value depends on the accuracy of built - in cr. operation example of return from l ow - p ower consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05631 rev * b page 109 of 128 mb9a b 40 nb series operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? when interrup t recoveries, the operation mode that cpu recoveries depend on the state before the low - power consumption mode transition. see c hapter 6 : low power consumption mode in fm3 family p eripheral m anual . 12.10.2 return f actor: reset the return time from low - power consu mption mode is indicated as follows. it is from releasing reset to starting the program operation. return c ount t ime ( v cc = 1.65 v to 3.6 v, v ddi = 1.1v to 1.3v, v ss = 0v, t a = - 40c to + 85 c ) parameter symbol value unit remarks typ max* sleep mode t rcnt 148 263 s high - speed cr timer mode, main timer mode, pll timer mode 148 263 s low - speed cr timer mode 258 483 s sub timer mode 322 516 s rtc/stop mode 278 523 s deep standby rtc mode deep standby stop mode 318 603 s when ram is off 278 523 s when ram is on *: the maximum value depends on the accuracy of built - in cr. i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05631 rev * b page 110 of 128 mb9a b 40 nb series operation example of return from l ow - p ower consumption mode (by initx) operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see c hapter 6 : low power con sumption mode and operations of standby modes in fm3 family p eripheral m anual . ? when interrupt recoveries, the operation mode that cpu recoveries depend on the state before the low - power consumption mode transition. see c hapter 6 : low power consumption mo de in fm3 family p eripheral m anual . ? the time during the power - on reset/low - voltage detection reset is excluded. see (6) power - on reset timing in 4. ac characteristics in electrical characteristics for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the h igh - speed cr r un mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait t ime or the m ain pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e
document number: 002 - 05631 rev * b page 111 of 128 mb9a b 40 nb series 13. ordering information part number on - chip flash memory on - chip sram package packing mb9afb41l b pmc1 - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 64 - pin (0.5mm pitch) , (lqd064) tray mb9afb42l b pmc1 - g - jne2 main: 128 kbyte work: 32 k byte 16 kbyte mb9afb44l b pmc1 - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41l b pmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 64 - pin (0. 6 5mm pitch) , (lqg064) mb9afb42l b pmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9afb44l b pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9af b 41l bqn - g - ave2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? qf n 64 - pin (0.5mm pitch) , ( vnc064 ) mb9af b 42l bqn - g - ave2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9af b 44l bqn - g - ave2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41m b pmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 80 - pin (0.5mm pitch) , (lqh080) mb9afb42m b pmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9afb44m b pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9af b 41m b pmc 1 - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 80 - pin (0. 6 5mm pitch) , (lqj080) mb9af b 42m b pmc 1 - g - jne2 main : 128 kbyte work: 32 kbyte 16 kbyte mb9af b 44m b pmc 1 - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41 m b bgl - ge1 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? pfbga 96 - pin (0.5mm pitch) , (fdg096) mb9afb42 m b bgl - ge1 main: 128 kbyte work: 32 kb yte 16 kbyte mb9afb44 m b bgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41n b pmc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 1 00 - pin (0.5mm pitch) , (lqi100) mb9afb42n b pmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9af b44n b pmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41n b p qc - g - jne2 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? qfp 1 00 - pin (0. 6 5mm pitch) , (pqh100) tray mb9afb42n b p qc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte mb9afb44n b p qc - g - jne 2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9afb41n b bgl - ge1 main: 64 kbyte work: 32 kbyte 16 kbyte plastic ? pfbga 1 12 - pin (0. 8 mm pitch) , ( lbc112 ) mb9afb42n b bgl - ge1 main: 128 kbyte work: 32 kbyte 16 kbyte mb9afb44n b bgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte
document number: 002 - 05631 rev * b page 112 of 128 mb9a b 40 nb series 14. package dimensions package type package code lqfp 100 lqi100 002 - 11500 * a n o t e s : 1 . a ll d i m e n s io n s a r e i n m i ll i m e t e r s . 2. d a t u m pla n e h i s lo c a t e d a t t h e bot t o m of t h e mold partin g li n e coi n c i d e n t w i t h w h e r e t h e l e a d e x i t s t h e body . 3 . d a tums a - b a n d d t o b e d e t e rmi n e d a t d a t u m p l a n e h . 4. to b e d e t e r m i n e d a t s e a t i n g plane c . 5 . d i m e n sio n s d1 a nd e 1 d o n ot i nc l ud e m ol d p r o t ru si o n . allowable protrusi o n is 0 . 25 mm p r e si d e . d i m e n s i o n s d 1 a n d e 1 i n c l u d e m o l d m i s m a t c h a n d a r e d e t e rmine d a t d a t u m plane h . 6 . d e t a i l s o f p i n 1 i d e n t i f i e r a r e o p t i o n a l b u t m u s t be l o c ate d w i t h i n th e zo n e i n d i c a t e d . 7 . r e g a r d l e s s of t h e r e l a t i v e s i z e o f t h e u p p e r a n d l o w e r b o d y s e c t i o n s . d i m e n s i o n s d 1 a n d e 1 a r e d e t e r m i n e d a t t h e larges t f e a t u r e o f t h e b o d y e x c l u s i v e o f m o l d f l a s h a n d g a te burrs . b u t i n clu d i n g a n y m i s m a t c h b e t w e e n t h e u p p e r a nd lowe r s e c t ion s of t h e mol d e r b o dy . 8 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b a r p r o t r u s i o n . t h e d a mba r p r o t r u s i o n ( s ) s h a l l n o t c a u s e t h e l e a d w i d t h to e x c e e d b m a x i m u m b y m o r e t h a n 0 . 0 8 m m . d a m b a r c a n n o t b e l o cated o n t h e l o w e r r a d i u s o r t h e l e a d f oot . 9. t h e s e d i m e n s ion s a p p l y t o t h e fla t s e c t i o n of the lea d b e t w e e n 0 . 10m m a n d 0.25 m m f r o m t h e lead tip . 10 . a 1 i s d e f i n e d a s t h e d i s t a n c e f r om t h e s e a t i n g p l a n e t o t h e low e s t p o i n t of t h e p a c k age body . d im e n s io n s symbol m in . n o m . max . a 1.7 0 a1 0.0 5 0.1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 6 . 00 bsc d 1 1 4 .00 bs c e 0 . 50 bsc e e1 l 0 .4 5 0 .6 0 0 .7 5 l1 0.3 0 0.5 0 0.7 0 1 6. 00 bsc 1 4. 00 bsc a a 1 0.25 0.0 8 c 1 100 d 1 d e 1 e e 4 4 0.0 8 c a - b d 7 5 seat i n g pla n e 0.2 0 c a - b d 0.1 0 c a - b d b se c t io n a-a ' c 9 a a ' 5 7 5 7 3 3 6 8 1 0 2 2 l1 l b d 1 d e 1 e 4 4 5 7 5 7 25 26 50 51 75 76 side v i ew top v i ew b o tt o m vie w d e t a il a 1 25 26 50 5 7 1 5 100 76 package ou t line, 1 00 le a d l q f p 14.0x14.0x1.7 mm lq i 100 r ev * a
document number: 002 - 05631 rev * b page 113 of 128 mb9a b 40 nb series package type package code qfp 100 pqh100 002 - 15156 ** d i mensi o n s s ymb o l m i n . n o m . max. a 3 . 3 5 a 1 0. 0 5 0. 4 5 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 1 1 0 . 2 3 d 2 3 . 9 0 b sc d 1 2 0 . 0 0 b sc e 0 .6 5 bsc e e1 l 0 . 7 3 0 . 8 8 1 . 0 3 l 1 1 . 9 5 r ef l 2 0.2 5 bs c 1 7 . 9 0 b sc 1 4 . 0 0 b sc 0 8 l 2 0 3 1 10 0 e b d1 d 5 7 4 e e 1 3 6 4 5 7 0 . 2 0 c a - b d 7 5 2 0 . 1 3 c a - b d 8 0 . 4 0 c a - b d 3 2 s e a t i n g p l an e b s e cti o n a - a ' c 9 s i d e vie w t o p vie w a a ' 0 . 1 0 c 1 0 d e t a il a 3 1 5 0 5 1 8 0 8 1 1 3 0 10 0 3 1 5 0 0 8 1 5 8 1 b o tt o m vie w package ou t line, 100 lea d q fp 20 . 00x14.00x3 . 35 mm p q h 100 r ev * *
document number: 002 - 05631 rev * b page 114 of 128 mb9a b 40 nb series package type package code lqfp 80 lqh080 002 - 11501 ** d i men s io n s m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 4 . 0 0 b s c . d 1 12.00 b s c . e 0 . 5 0 bs c e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 4 . 0 0 b s c . 1 2 . 0 0 b s c . s y m b o l b o t t o m vie w a a 1 0 . 2 5 1 8 0 d 1 d e b d 0. 2 0 c a - b d 0. 1 0 c a - b d 0. 0 8 c a - b d e e 1 4 5 7 3 4 5 7 3 8 7 5 2 1 0 b s e c t i o n a - a ' c 9 2 s ea t i n g p l an e 0. 0 8 c a a ' 6 l 1 l s i de vie w t o p vie w 2 0 2 1 4 0 1 4 0 6 6 1 0 6 1 4 8 0 6 1 2 1 4 0 1 2 0 package ou t line, 80 le a d lq f p 12.0x12.0x1.7 mm lq h 080 r e v * *
document number: 002 - 05631 rev * b page 115 of 128 mb9a b 40 nb series package type package code lqfp 80 lqj080 002 - 14043 ** d i mensions s y m b o l m i n . n o m . m ax . a 1 . 7 0 a 1 0 . 0 0 0 . 2 0 b 0 .1 6 0 .38 c 0 .0 9 0 .20 d 1 6.0 0 b s c d 1 1 4 . 0 0 bs c e 0.65 bsc e e 1 l 0 .4 5 0 .6 0 0 .75 l 1 0 . 3 0 0 . 5 0 0 . 7 0 1 6 . 0 0 bs c 1 4 . 0 0 bs c 0 . 3 2 0 8 d 1 d e 0 2 1 80 e e 1 4 5 7 4 5 7 3 0.2 0 c a - b d 3 b 0.1 0 c a - b d 8 7 5 2 2 a a ' s e a t i n g p l an e a a 1 0.2 5 1 0 b s e c t i o n a - a ' c 9 l1 l 6 0.1 0 c dd d c a - b d 1 21 40 41 60 61 2 0 2 1 4 0 0 6 1 4 8 0 6 1 14.0x14.0x1.7 mm l q j 080 r ev * * package ou t line, 8 0 lea d lq f p
document number: 002 - 05631 rev * b page 116 of 128 mb9a b 40 nb series package type package code lqfp 64 lqd064 002 - 11499 ** d i m e nsion s s y m b o l min . n o m . max . 0 7 . 1 a a1 0.0 0 0.2 0 b 0.1 5 0. 2 c 0.0 9 0.2 0 d 12 . 00 bsc. d 1 10 . 00 bsc. e 0 .50 bsc e e1 l 0.4 5 0.6 0 0.7 5 l 1 0.3 0 0.5 0 0.7 0 12 . 00 bsc. 10 . 00 bsc. d 1 d e 1 1 6 6 4 4 5 7 e e 1 4 5 7 3 6 3 0.2 0 c a - b d b 0.1 0 c a - b d 0.0 8 c a - b d 8 7 5 2 a a 1 0 . 25 10 b se c t ion a-a ' c 9 l1 l 2 a a ' s e a t i n g plan e 0.0 8 c side v i e w top v i e w b o tt o m vie w 1 7 3 2 3 3 4 8 4 9 1 1 6 1 7 3 2 3 3 4 8 6 4 4 9 package ou t line, 64 le a d lq f p 10 . 0x10 . 0x1 . 7 mm l q d064 re v * *
document number: 002 - 05631 rev * b page 117 of 128 mb9a b 40 nb series package type package code lqfp 64 lqg064 002 - 13881 ** dimensi o n sym b o l m i n . no m . m ax . a 1.7 0 a 1 0.0 0 0.2 0 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 0 9 0 . 20 d 14.00 bsc d 1 12.00 bsc e 0.65 bsc e e 1 l 0.4 5 0.6 0 0.7 5 l1 0.3 0 0.5 0 0.7 0 14.00 bsc 12.00 bsc 0 d 1 d e 1 16 64 e e 1 4 5 7 4 5 7 3 3 0.20 c a - b d b 0.10 c a - b d 0.13 c a - b d 8 7 5 2 2 0.10 c a a' s eati n g pla n e b s ec t i on a - a' c 9 a a 1 0.2 5 1 0 l1 l s i d e vie w t o p v i e w b o tt o m vie w 17 32 33 48 49 1 16 17 32 64 49 8 4 3 3 12 . 0x12 . 0x1 . 7 m m lq g 064 r ev * * package ou t line, 6 4 lea d lq f p
document number: 002 - 05631 rev * b page 118 of 128 mb9a b 40 nb series package type package code qfn 64 vnc064 002 - 13234 ** dimen s io n s n o m. m i n . b e 6.00 bs c 9.00 bs c d a 1 a 9.00 bs c 0.00 sym b o l ma x . 0.90 0.05 0.50 bs c l 0.35 0.45 0.40 0.2 0 0.2 5 0.30 e d 2 2 6.00 bs c e n 64 0.20 ref r n d 1 6 b i late r al c o p l a n a r it y zo n e a p pli e s to the exposed heat p i n # 1 i d o n t o p w i l l b e l o c a t e d w i t h i n t h e i n d i c a t e d z o n e. m a x i m u m a l l o w a b l e b u r r i s 0 . 0 7 6 m m i n a l l d i r e c t i o n s. d i m e n s i o n " b " a p p l i e s t o m e t a l l i z e d t e r m i n a l a n d i s m eas ur ed n i s t h e t o t a l n u m b e r o f t e r m i n a l s . a l l d i m e n sio n s a r e i n m i l l i m e t e r s . d i m e n s i o n i n g a n d t o l e r a n c i n g c o n f o r m s t o a s m e y 1 4 . 5 m-1994 . n o tes: ma x . p a c k age w a r p age i s 0.05mm . 8 7 . 6 . 5 1 . 4 3 . 2 . 9 h a s t h e optio n a l r a d i u s o n t h e ot h e r e n d of t h e te rm i n a l , t h e d i me n sio n " b " s h o uld n ot b e me a s u r e d i n t h at r a d i u s a r ea. n d r e f e r s to t h e n u m b e r of t e rmi n als o n d s i d e or e side . s i n k slug a s w e ll a s t h e t e rminals . be tw een 0 . 15 and 0 . 30mm f r o m t erm i n a l ti p . if t h e t e rm i n a l s i de vie w b o tt om vie w t o p vie w d a e b 0. 1 0 c 2 x 0. 1 0 c 2 x 0. 1 0 c a a 1 0. 0 5 c c seating plan e d2 e 2 0. 1 0 c a b 0. 1 0 c a b 1 6 4 e b 0. 1 0 c a b 0. 0 5 c ( n d - 1 ) e index m ar k 8 4 5 l 9 1 6 1 7 3 2 8 4 3 3 4 9 6 4 4 9 1 6 3 3 1 4 8 1 7 3 2 p a c k a ge o ut l i n e , 64 l ea d q f n 9 . 0 x 9 . 0 x0 . 9 m m v nc 0 64 6 . 0 x6 . 0 m m e pa d ( s aw n ) r e v*. *
document number: 002 - 05631 rev * b page 119 of 128 mb9a b 40 nb series package type package code fbga 112 lbc112 002 - 13225 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 3 5 0 . 0 0 0 . 8 0 bs c 0 . 8 0 bs c 0 . 4 5 11 2 1 1 0 . 5 5 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 2 5 m i n . - 8 . 0 0 bs c 8 . 0 0 bs c 1 1 1 0 . 0 0 bs c 1 0 . 0 0 bs c n o m . - 1 . 4 5 0 . 4 5 m ax . s e 0 . 0 0 0 . 3 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0 . 20 c 2 x b 0 . 20 c 2 x i n d e x ma rk pin a 1 c o rne r 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 11 2 x b 0 . 08 c a b 5 6 6 s i d e vie w 0 . 10 c c d e t a il a b o tt o m vie w t o p vie w d e t a i l a 10 . 00x10 . 00 x1.45 mm l b c 112 r ev * * package ou t line, 11 2 ball f b g a
document number: 002 - 05631 rev * b page 120 of 128 mb9a b 40 nb series package type package code fbga 96 fdg096 002 - 13224 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 2 0 0 . 0 0 0 . 5 0 bs c 0 . 5 0 bs c 0 . 3 0 9 6 1 1 0 . 4 0 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 1 5 m i n . - 5 . 0 0 bs c 5 . 0 0 bs c 1 1 6 . 0 0 bs c 6 . 0 0 bs c n o m . - 1 . 3 0 0 . 3 5 m ax . s e 0 . 0 0 0 . 2 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0.2 0 c 2 x b 0.2 0 c 2 x i n d e x m a r k p i n a 1 corner 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 96 x b 0.0 5 c a b 5 6 6 s i de vie w 0.2 0 c 0.0 8 c c deta i l a b o t t o m vie w t o p vie w deta i l a 6.0x6.0x1.3 m m f d g 096 r ev * * package ou t line, 9 6 ball f bga
document number: 002 - 05631 rev * b page 121 of 128 mb9a b 40 nb series 15. errata this chapter describes the errata for mb9ab40n, mb9ab40na and mb9ab40nb series . details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypres s sales representative if you have questions. 15.1 part numbers affected part number initial revision mb9afb41npmc - g - jne2, mb9afb42npmc - g - jne2, mb9afb44npmc - g - jne2, mb9afb41npqc - g - jne2, mb9afb42npqc - g - jne2, mb9afb44npqc - g - jne2, mb9afb41nbgl - ge1, mb9afb42nbgl - ge1, mb9afb44nbgl - ge1, mb9afb41mpmc - g - jne2, mb9afb42mpmc - g - jne2, mb9afb44mpmc - g - jne2, mb9afb41mpmc1 - g - jne2, mb9afb42mpmc1 - g - jne2, mb9afb44mpmc1 - g - jne2, mb9afb41mbgl - ge1, mb9afb42mbgl - ge1, mb9afb44mbgl - ge1, mb9afb41lpmc1 - g - jne2, mb9afb42lpmc1 - g - jne2, mb9af b44lpmc1 - g - jne2, mb9afb41lpmc - g - jne2, mb9afb42lpmc - g - jne2, mb9afb44lpmc - g - jne2, mb9afb41lqn - g - ave2, mb9afb42lqn - g - ave2, mb9afb44lqn - g - ave2 rev. a mb9afb41napmc - g - jne2, mb9afb42napmc - g - jne2, mb9afb44napmc - g - jne2, mb9afb41napqc - g - jne2, mb9afb42napqc - g - jne2 , mb9afb44napqc - g - jne2, mb9afb41nabgl - ge1, mb9afb42nabgl - ge1, mb9afb44nabgl - ge1, mb9afb41mapmc - g - jne2, mb9afb42mapmc - g - jne2, mb9afb44mapmc - g - jne2, mb9afb41mapmc1 - g - jne2, mb9afb42mapmc1 - g - jne2, mb9afb44mapmc1 - g - jne2, mb9afb41mabgl - ge1, mb9afb42mabgl - ge1, mb 9afb44mabgl - ge1, mb9afb41lapmc1 - g - jne2, mb9afb42lapmc1 - g - jne2, mb9afb44lapmc1 - g - jne2, mb9afb41lapmc - g - jne2, mb9afb42lapmc - g - jne2, mb9afb44lapmc - g - jne2, mb9afb41laqn - g - ave2, mb9afb42laqn - g - ave2, mb9afb44laqn - g - ave2 rev. b mb9afb41nbpmc - g - jne2, mb9afb42nbp mc - g - jne2, mb9afb44nbpmc - g - jne2, mb9afb41nbpqc - g - jne2, mb9afb42nbpqc - g - jne2, mb9afb44nbpqc - g - jne2, mb9afb41nbbgl - ge1, mb9afb42nbbgl - ge1, mb9afb44nbbgl - ge1, mb9afb41mbpmc - g - jne2, mb9afb42mbpmc - g - jne2, mb9afb44mbpmc - g - jne2, mb9afb41mbpmc1 - g - jne2, mb9afb42mbp mc1 - g - jne2, mb9afb44mbpmc1 - g - jne2, mb9afb41mbbgl - ge1, mb9afb42mbbgl - ge1, mb9afb44mbbgl - ge1, mb9afb41lbpmc1 - g - jne2, mb9afb42lbpmc1 - g - jne2, mb9afb44lbpmc1 - g - jne2, mb9afb41lbpmc - g - jne2, mb9afb42lbpmc - g - jne2, mb9afb44lbpmc - g - jne2, mb9afb41lbqn - g - ave2, mb9afb42 lbqn - g - ave2, mb9afb44lbqn - g - ave2, 15.2 qualification status product status: in production ? qual. 15.3 errata summary this table defines the errata applicability to available devices.
document number: 002 - 05631 rev * b page 122 of 128 mb9a b 40 nb series items p art number silicon revision fix status [1] flash lower bank read dur ing write refer to 15.1 initial rev. fixed in rev. a [2] flash read during write & erase suspend refer to 15.1 initial rev. fixed in rev. a [3] regulator issue refe r to 15.1 initial rev., rev. a fixed in rev. b [4] hdmi - cec arbitration lost issue refer to 15.1 initial rev., rev. a fixed in rev. b [5] hdmi - cec polling message i ssue refer to 15.1 initial rev., rev. a , rev. b next silicon is not planned 1. flash lower bank read during write ? problem definition during writing (programming) to flash memory of an upper bank, flash memory of a lower bank could not be read at a specific timing in some operation combinations. ? parameters affected n/a ? trigger condition(s) this issue may happen when read data or fetch instruction from the flash memory lower bank (smaller sector), while a write (program) operation to the flash memory upper bank (larger sector) is in progress. ? scope of impact instructions could not be fetched (read) correctly from the lower bank, and then execution of the (corrupted) instructions ma y cause a hard fault or run - away . if an instruction in ram reads a data from the lower bank while writing to the upper bank, an incorrect value might be read. ? workaround to rewrite the upper bank of flash memory, put the write instruction in ram instead of the lower bank and execute it f rom the ram. do not access the lower bank until the write operation is completed (rdy=1). especially to avoid a vector fetch from the lower bank of the flash memory by an interrupt occurred, the interrupt should be prohibited or the vector address should be set to ram by the vector table offset register. ? fix status this issue was fixed in rev. a. 2. flash read during write & sector erase suspend ? problem definition when writing is executed during sector erase suspend, flash memory could not be read correct ly at a specific timing. ? parameters affected n/a ? trigger condition(s) this issue may happen when read data or fetch instruction from the flash memory bank (higher or lower), while a write (program) operation is in progress to the opposite bank which has a sector erase suspended. the following flow could not be executed correctly. (a) erase a sector of a bank (b) suspend the sector erase operation (c) write to a different sector of the bank (d) execute an instruction or read data in the opposite bank
document number: 002 - 05631 rev * b page 123 of 128 mb9a b 40 nb series ? scope of impact ? instruc tions could not be fetched (read) correctly, and then execution of the (corrupted) instructions may cause a hard fault or run - away. if an instruction in ram reads a data from the bank, an incorrect value might be read. ? workaround do not execute the write o peration to a different sector in the same bank at sector erase suspend. ? fix status this issue was fixed in rev. a. 3. regulator issue ? problem definition the regulator does not get initialized while internal power - up sequence. ? parameters affected n/a ? trigg er condition(s) this issue rarely happens depending on states of internal circuits which the user cannot control. ? scope of impact mcu does not start operation if this issue occurs. ? workaround this error cannot be avoided by any software. ? fix status this is sue was fixed in rev. b. 4. hdmi - cec arbitration lost issue ? problem definition large external load on cec bus may cause arbitration lost. ? parameters affected n/a ? trigger condition(s) the arbitration lost detection mechanism samples outputting signals and d etermines that arbitration lost occurs if sampled signals do not match the outputting signals. the large external load on the cec bus increases slew rate of the signals. the increased slew rate makes the mismatch between outputting signals and sampled sign als and the mismatch misleads mcu that arbitration lost occurs. ? scope of impact once the arbitration lost is detected, the cec aborts the transmission. any transmission cannot be completed. ? workaround ? this error cannot be avoided by any software. reduce th e external load. ? fix status ? this issue was fixed in rev. b.
document number: 002 - 05631 rev * b page 124 of 128 mb9a b 40 nb series 5. hdmi - cec polling message issue ? problem definition error#1) while mcu sends a polling message, it always returns a nack to a message coming to the mcu from another node. error#2) mcu always wai ts for 7 - bit signal free on cec line before it drives the line even when the last line initiator was another node. ? parameters affected n/a ? trigger condition(s) this error always happens. ? scope of impact mcu does not reply properly to another node. ? workarou nd the software workaround is applied to error #1. 1. store 0x0 to sfree register. 2. monitor cec line with gpio and wait until 1 lasts for the signal free time. 3. store frame data to txdata register and store 0x0f to rcadr1 or rcadr2 register. it sends a message after 3~4 clocks of 32.768 khz clock when txdata is stored 0x0f. if the device receives a frame from another node within 2~3 clocks after storing txdata, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after stor ing txdata, the arbitration lost occurs. in these cases: 4 - a - 1. set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - a - 2. return back to step 2 above if the device receives a frame from another node within 1~2 clocks after storing txdata, take the se steps. 4 - b - 1. monitor cec line with gpio after 50us from storing txdata 4 - b - 2. set txen to 1 - > 0 - > 1 immediately when gpio finds state low on the cec line 4 - b - 3. set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - b - 4. return back to step 2 above for error #2, there is no software workaround, but signal free time of fixed 7 - bit does not violate hdmi - cec specification. the specification says signal free time must be more than and equals to 5 - bit. ? fix status the user uses the workaround to avoi d the issue. the next silicon fixing the issue is not planned.
document number: 002 - 05631 rev * b page 125 of 128 mb9a b 40 nb series 16. major changes spansion publication number: ds706 - 00034 page section change results revision 2.0 2 ? feature ? on - chip memories revised the descriptions of [flash memory]. ? usb interface revised the descriptions of [usb function ]. 6 ? unique id added the descriptions of "unique id". 7 ? product lineup ? function 52 ? handling devices added the descr iptions. 5 7 ? memory map ? memory map (2) 6 2 ? pin status in each cpu state ? list of pin status revised the pin status type of "i". 70 ? electrical characteristics 3.dc characteristics (1) current rating ? revised the descriptions of power supply current . ? added the "flash memory write/erase current". ? added the foot note. 7 4 5.ac characteristics (3) built - in cr oscillation characteristics ? built - in high - speed cr revised the table and the footnote. 7 8 , 7 9 (7) external bus timing ? separate bus access asynchronous sram mode revised the table and the figure. 80 ? separate bus access synchronous sram mode 8 5 , 8 7 , 8 9 , 9 1 (9) csio timing ? revised the title to "csio timing". ? revised the note. 9 4 (11) i 2 c timing revised the footnote. 97 6 . 12 - bit a/d converter ? electrical characteristics for the a/d converter ? revised the paramet e r . ? revised the symbol. ? corrected the value. 99 ? definition of 12 - bit a/d converter terms ? revised the paramet e r . ? revised the symbol. 104 8 . low - voltage detection characteristics (1) low - voltage detection reset ? corrected "condition s " and "value" in the table. ? added the item. ? added the footnote . 105 (2) interrupt of low - voltage detection added the item. revision 2.1 - - company name and layout design change revision 3.0 - - corrected the series name. mb9ab40na series mb9ab40nb series - - corrected the product name as follows. mb9afb44lb, mb9afb42lb, mb9afb41lb mb9afb44mb, mb9afb42mb, mb9afb41mb mb9afb44nb, mb9afb42nb, mb9afb41nb 2 ? features ? external bus interface added the item. ? maximum area size : up to 256 mb ytes 3 ?multi - function serial interface corrected the description of "i 2 c" 7 ? product lineup ? function added the footnote 55 ? block diagram ? corrected the figure 56 ? memory map ? ?memory map (1) ? corrected the address "external device area" 68 ? electrica l characteristics ? 2.recommended operating conditions add the footnote 69,70 3. dc characteristics (1) current rating ? corrected the condition ? delete the minmun value ? corrected the remarks ? add the footnote 92 (9) csio timing ? synchronous serial (spi=1, scinv=1) corrected the figure of "ms bit=1"
document number: 002 - 05631 rev * b page 126 of 128 mb9a b 40 nb series page section change results (9) csio timing ? external clock(ext=1):asyntironous only ? corrected the figure 94 (12) i 2 c timing corrected the description as follows. ? typical mode standard - mode ? high - speed mode fast - mode 97 5.12 - bit a/d converter ? electrical characteristics for the a/d converter ? corrected the terminal name an00 ~ an23 anxx ? corrected the minmum value of "sampling time" ? corrected the max and mi n value of "state transition time to oprerationpermission" ? corrected the footnote 107 ? ordering informaton ? corrected the "part number" revision 4.0 2 ? features l usb interface added the description of pll for usb 57 ? memory map memory map(2) added th e summary of flash memory sector and the note 69 - 71 ? electrical characteristics 3. dc characteristics (1) current rating changed the table format added main timer mode current moved a/d converter current 72 ? electrical characteristics 3. dc chara cteristics (2) pin characteristics added input leak current of cec pin at power off. 76 ? electrical characteristics 5. ac characteristics (4 - 1) operating conditions of main and usb pll (4 - 2) operating conditions of main pll added the figure of main pll co nnection and usb pll connection 77 ? electrical characteristics 5. ac characteristics (6) power - on reset timing added time until releasing power - on reset changed the figure of timing 86 - 93 ? electrical characteristics 5. ac characteristics (9) csio/u art timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 98 ? electrical characteristics 6. 12bit a/d converter added the typical v alue of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage added conversion time at avcc < 2.7v 108 - 111 ? electrical characteristics 10. return time from low - power consumption mode added return t ime from low - power consumption mode 112, 113 ? ordering information ? changed notation of part number note: please see document history about later revised information.
document number: 002 - 05631 rev * b page 127 of 128 mb9a b 40 nb series document history document title: mb9ab4 0 nb series 32 - bit arm? cortex? - m3 fm3 microcon troller document number: 002 - 05631 revision ecn orig. of change submission date description of change ** - akih 06/10/2015 migrated to cypress and assigned document number 002 - 05631. no change to document contents or format. *a 5120116 akih 02/15/2016 updated to cypress template * b 5534251 yska 07/2 6 6
document number: 002 - 05631 rev * b july 26, 2017 page 128 of 128 mb9a b 40 nb series sales, solutions, and legal information wo rldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress l ocations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buf fers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot m emory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypr ess.com/usb wireless/rf cypress.com/wireless psoc? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support arm an d cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 201 2 - 2017. this documen t is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress). this docume nt, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, tr ademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not ot herwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non - exc lusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only intern ally within your organiza tion, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use o n cypress hardware product units, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely f or use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is p rohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this doc ument or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly des ign, program, and test the functionality and safety of any application made of this information and any resulting product. c ypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the op eration of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution con trol or hazardous substances management, or other uses whe re the failure of the device or system could cause personal injury, death, or property damage (unintended uses). a critical compo nent is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and he reby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress produc ts. you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintend ed uses of cypress products. cypress, the cypress l ogo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners.

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